The fact that there are more embedded computers than general-purpose computers and that we are impacted by hundreds of them every day is no longer news. What is news is that their increasing performance requirements, complexity and capabilities demand a new approach to their design. 

Fisher, Faraboschi, and Young describe a new age of embedded computing design, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design. They demonstrate why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses. These elements must be unified in a system design with high-performance processor architectures, microarchitectures and compilers, and with the compilation tools, debuggers and simulators needed for application development. 

In this landmark text, the authors apply their expertise in highly interdisciplinary hardware/software development and VLIW processors to illustrate this change in embedded computing. VLIW architectures have long been a popular choice in embedded systems design, and while VLIW is a running theme throughout the book, embedded computing is the core topic. Embedded Computing examines both in a book filled with fact and opinion based on the authors many years of R&D experience.

? Complemented by a unique, professional-quality embedded tool-chain on the authors' website, http://www.vliw.org/book
? Combines technical depth with real-world experience 
? Comprehensively explains the differences between general purpose computing systems and embedded systems at the hardware, software, tools and operating system levels. 
? Uses concrete examples to explain and motivate the trade-offs.

Table of Contents

Preface
Chapter 1: An Introduction to Embedded Processing
Chapter 2: An Overview of VLIW and ILP
Chapter 3: An Overview of ISA Design
Chapter 4: Architectural Structures in ISA design 
Chapter 5: Microarchitecture Design 
Chapter 6: System Design and Simulation
Chapter 7: Embedded Compiling and Toolchains 
Chapter 8: Compiling for VLIWs and ILP 
Chapter 9: The Run-time System 
Chapter 10: Application Design and Customization 
Chapter 11: Application Areas 
Appendix A: The VEX System 
Appendix B: Glossary 
Appendix C: Bibliography

Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools

A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus 102 through a bus bridge 113 . A first set of processing resources operate from high speed bus 102 and includes an external memory interface 108 , a direct memory access engine 105 for controlling the exchange of information through memory interface 108 , and a boot memory 104 for storing boot code. A second set of processing resources operate from peripheral bus 103 and includes an interrupt controller 115 for issuing interrupt requests to microprocessor 101 , a set of programmable timers 117 for generating timed interrupt signals, and a phase locked loop 131 for generating timing signals.

System-on-a-chip

The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus architecture (CCBA). The performance of these architectures is evaluated using applications from wireless communications-an Orthogonal Frequency Division Multiplexing (OFDM) transmitter-and from video processing-an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.

A comparison of five different multiprocessor SoC bus architectures

The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus I1 Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and Coreconnect Bus architecture (CCBA). The pedormance of these architectures is evaluated using applications from wireless communications - an Orthogonal Frequency Division Multiplexing (OFDM) transmitter - and from video processing - an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEGZ decoder, respectively.

A Comparison of Five Different Mu It i processor SoC Bus Architectures

This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for minimum energy is formulated as a minimum-exchange bus split problem, which is shown to be NP-complete. The problem is solved heuristically by using a maximum-weight matching algorithm and combinatorial search. Experimental results show that the energy saving of split-bus architecture compared to monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split-bus. The proposed split-bus architecture can be extended to multiway split-bus architecture when large numbers of modules are to be connected.

/pdf/architectural-energy-optimization-by-bus-splitting-35ngq5x8io.pdf

Architectural energy optimization by bus splitting

A bus architecture that provides high performance while scaling across a range of chip sizes is described. The system on a chip design in which it has been implemented includes both a dedicated processor with a set of embedded system peripherals and system support logic that may be reconfigured by a user in the field. Multiple masters and slaves are provided for in the architecture and included in the dedicated portion of this chip. Designers configure additional bus slave peripherals and support functions in the programmable logic. Dedicated structures extend the bus throughout the user-configurable system logic. The bus is pipelined, uses OR gates, and has separate read and write data. The bus pipeline registers are distributed to provide predictable performance and a synchronous interface to the designer. Bus protocol decoders are also distributed throughout the logic. These protocol decoders handle the complexities of pipelining for the designer. Virtual bus sockets provide all of the physical signals necessary to interface registers to the bus for single-cycle read and write transactions. The physical characteristics and design methods involved in the design of this system on a chip as well as those of the application environment all influenced the design tradeoffs in this architecture.

S. Winegarden

Papers

Bus architecture of a system on a chip with user-configurable system logic