This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E Starter kit (XC3S500E-FG320) exceeds those of similar or greater resources architectures. The proposed architecture reduces the resources available on target device by 50%.

An efficient FPGA implementation of MRI image filtering and tumor characterization using Xilinx system generator

Ransomware Detection using Random Forest Technique

ASL, CNN, Accuracy. An American Sign Language (ASL) is a complex language. It is depending on the special gesture stander of marks. These marks are represented by hands with assistance by facial expression and body posture. ASL is the main communication language of deaf and people who have hard hearing from North America and other parts of the world. In this paper, Gesture recognition is proposed of static ASL using Deep Learning. The contribution consists of two solutions to the problem. The first one is resized with Bicubic static ASL binary images. Besides that, good recognition results in of detection the boundary hand using the Robert edge detection method. The second solution is to classify the 24 alphabets static characters of ASL using Convolution Neural Network (CNN) and Deep Learning. The classification accuracy equals to 99.3 % and the error of loss function is 0.0002. According to 36 minutes with 15 seconds of elapsed time result and 100 iterations. The training is fast and gives the very good results, in comparison with other related works of CNN, SVM, and ANN for training. How to cite this article: A. A. Abdulhussein and F. A. Raheem, “Hand gesture recognition of static letters American sign language (ASL) using deep learning,” Engineering and Technology Journal, Vol. 38, No. 06, pp. 926-937, 2020. DOI: https://doi.org/10.30684/etj.v38i6A.533

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Hand Gesture Recognition of Static Letters American Sign Language (ASL) Using Deep Learning

The number of connected mobile devices and Internet of Things (IoT) is growing around us, rapidly. Since most of people's daily activities are relying on these connected things or devices. Specifically, this past year (with COVID-19) changed daily life in abroad and this is increased the use of IoT-enabled technologies in the health sector, work, and play. Further, the most common service via using these technologies is the localization/positioning service for different applications including: geo-tagging, billing, contact tracing, health-care system, point-of-interest recommendations, social networking, security, and more. Despite the availability of a large number of localization solutions in the literature, the precision of localization cannot meet the needs of consumers. For that reason, this paper provides an in-depth investigation of the existing technologies and techniques in the localization field, within the IoT era. Furthermore, the benefits and drawbacks of each technique with enabled technologies are illustrated and a comparison between the utilized technologies in the localization is made. The paper as a guideline is also going through all of the metrics that may be used to assess the localization solutions. Finally, the state-of-the-art solutions are examined, with challenges and perspectives regarding indoors/outdoors environments are demonstrated. 

A Comprehensive Review of Indoor/Outdoor Localization Solutions in IoT era: Research Challenges and Future Perspectives

3-D raw data collections introduce noise and artifacts that need to be recovered from degradation by an automated filtering system before further machine analysis. Serving this goal, five performance-efficient FPGA-prototyped processors are devised to realize parallel 3-D “filtering algorithm”. These parallel processors tackle the major bottlenecks and limitations of existing multiprocessor systems in input volumetric data, processing word-length, output boundary conditions and inter-processor communications. Then, greyscale 256×256×20 MRI case study are efficiently filtered and improved by a class of common convolution operators and their developed ones respectively. Analytically, the performance of the five implemented processors are evaluated in term of area, speed, dynamic power, and throughput. All five processors efficiently perform in high real-time throughput up to (114 VPS), lowest power consumption of down to (64 mW) at maximum operating frequency. The devised processors can be embedded in mobile MRI or fMRI scanner and as a pre-filtering stage in any portable automated fMRI systems.

Performance-vetted 3-D MAC processors for parallel volumetric convolution algorithm: A 256×256×20 MRI filtering case study

Currently, Field Programmable Gate Array (FPGA) goes beyond the low-level line-by-line hardware description language programming in implementing parallel multidimensional image filtering algorithms. High-level abstract hardware-oriented parallel programming method can structurally bridge this gap. This paper proposes a first step toward such a method to efficiently implement Parallel 2-D MRI image filtering algorithms using the Xilinx system generator. The implementation method consists of five simple steps that provide fast FPGA prototyping for high performance computation to obtain excellent quality of results. The results are obtained for nine 2-D image filtering algorithms. Behaviourally, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are targeted to achieve; lower power consumption of (1.57 W) and down to (0.97 W) respectively at maximum sampling frequency of up to (230 MHZ). Then, one of the nine MRI image filtering algorithms, has empirically improved to generate an enhanced MRI image filtering with moderate lower power consumption at higher maximum frequency.

Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator

In this work, Design of second order sliding mode control has been developed to control the diabetic glucose concentration level under disturbing meal has been controlled using three sliding mode controllers. A comparative study of three sliding mode controllers is made in terms of robustness characteristics due to meal feeding. The first is the classical sliding mode controller, the second is integral sliding mode controller and the third is the second order sliding mode controller. Due to their characteristic features of disturbance rejection, all the three sliding mode controllers are presented here for comparison. The Bergman minimal mathematical model is used to describe the dynamic behavior of blood glucose concentration due to insulin regulator injection. Simulations, based on MATLAB/Simulink, were performed to verify the performance of each controller. It has been shown that integral and second order sliding mode controllers are the best of all in terms of disturbance rejection capability.

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Design of second order sliding mode for glucose regulation systems with disturbance

Parallel 1-D signal filtering algorithm is implemented as a parameterized efficient FPGA-based architecture using Xilinx System Generator. The implemented algorithm is a linear indirect filters achieved by a parallel FFT/point-by-point complex inner product/ IFFT convolution unit array. The implemented architecture manifests a 38 % higher performance per Watt at maximum frequency. The parameterized implementation provides rapid system-level FPGA prototyping and operating frequency portability. Consequently, the results are obtained independent of the two targeted Virtex-6 FPGA boards, namely xc6vlX240Tl–1lff1759 and xc6vlX130Tl–1lff1156, to achieve lower power consumption of (1.6 W) and down to (0.99 W) respectively at a maximum frequency of up to (216 MHz). A case study of real-time speech filtering shows excellent performance results of power consumption down to (0.99W) at maximum frequency of up to (216 MHz).

Parameterized FPGA-based architecture for parallel 1-D filtering algorithms

A parallel 4D fMRI filtering algorithm is proposed to overcome the bottlenecks of large 4D volumetric fMRI data and its overlapping segments by input decimation, multidimensional intensive computation by parallel processing and the boundary conditions by output interpolation. Three spatial convolution architectures implement this parallel multidimensional filtering algorithm in Virtex-6 FPGA board, as automated 4D fMRI filtering systems. These three automated filtering systems are devised as “plug and develop” processors to filter any 4D volumetric data. Then, two sets of generic Edge and noise smoothing filtering operators are prototypically plugged and developed to be improved for filtering a dementia case study of color 256 × 256 × 4 × 3 volumetric fMRI. Accordingly, performance indices of the three architectures are evaluated as a complete package of area, speed, dynamic power, and throughput. Significant improvements have been achieved in keeping a stable speed, decreasing power consumption and increasing throughput in color fMRI filtering applications. All three architectures have an operating (225 MHz) maximum frequency. The power consumption improved more than two-fold using architecture 2 compared to 3. The highest throughput is achieved by architectures 2 and 3 almost (2.5) times than that of architecture 1. Evidently, all three architectures are performance-aware processors, and architecture 2 is optimal.

Sami Hasan

Papers

Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator

Design of second order sliding mode for glucose regulation systems with disturbance

Performance-vetted 3-D MAC processors for parallel volumetric convolution algorithm: A 256×256×20 MRI filtering case study

Parameterized FPGA-based architecture for parallel 1-D filtering algorithms

Performance-Aware Architectures for Parallel 4D Color fMRI Filtering Algorithm: A Complete Performance Indices Package