http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

In this paper we present a reconfigurable routing algorithm for a 2D-mesh network-on-chip (NoC) dedicated to fault- tolerant, massively parallel multi-processors systems on chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router).

/pdf/a-reconfigurable-routing-algorithm-for-a-fault-tolerant-2d-1r0vyhd8pi.pdf

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

Methods for fault tolerance in networks-on-chip

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

the occurrence of congestion in on-chip networks can severely degrade the performance due to increased message latency. In mesh topology, minimal methods can propagate messages over two directions at each switch. When shortest paths are congested, sending more messages through them can deteriorate the congestion condition considerably. In this paper, we present an adaptive routing algorithm for on-chip networks that provide a wide range of alternative paths between each pair of source and destination switches. Initially, the algorithm determines all permitted turns in the network including 180-degree turns on a single channel without creating cycles. The implementation of the algorithm provides the best usage of all allowable turns to route messages more adaptively in the network. On top of that, for selecting a less congested path, an optimized and scalable learning method is utilized. The learning method is based on local and global congestion information and can estimate the latency from each output channel to the destination region.

/pdf/haraq-congestion-aware-learning-model-for-highly-adaptive-42mcjwsv97.pdf

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks

We present an extension of Duato's necessary and sufficient condition a routing function must satisfy in order to be deadlock-free, to support environment constraints inducing extra-dependencies between messages. We also present an original algorithm to automatically check the deadlock-freeness of a network with a given routing function. A prototype tool has been developed and automatic deadlock checking of large scale networks with various routing functions have been successfully achieved. We provide comparative results with standard approach, highlighting the benefits of our method.

/pdf/a-tool-for-automatic-detection-of-deadlock-in-wormhole-jzdsqnv79t.pdf

A tool for automatic detection of deadlock in wormhole networks on chip

Deadlocks are an important issue in wormhole networks and a lot of works have been done on deadlock avoidance. Sufficient and necessary deadlock-freeness conditions have been proposed and used to build deadlock-free wormhole networks. But none of these works provide an efficient way to verify if a given network is deadlock-free. The present article proposes a new sufficient and necessary condition associated with a polynomial algorithm to check if a given network is deadlock-free. This new algorithm identifies {\em escape paths} from channels that are involved in circular dependencies. Identifying escape paths can be easily done by studying strongly connected components of the dependency graph instead of studying individually each cycle. The proposed algorithm has been implemented in a tool for automatic detection of deadlocks in wormhole networks (ODI). ODI has been used to establish the deadlock-freeness of complex realistic networks and networks with defective routers.

A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks

It is well known that localisation is a fundamental issue for many wireless network applications Without the need of additional ranging devices, the range–free localisation technology is a cost–effective solution for low–cost indoor and outdoor wireless sensor networks However, we noted that most existing algorithms were only studied using tools like MATLAB neglecting possible problems in a real wireless network context such as frame collision and node synchronisation Thus, we propose an adaptive range–free localisation protocol (ALP) based on IEEE 802154 standard, which can evaluate localisation algorithms Using our localisation protocol, we investigate and compare the performance of our new approach to some existing range–free algorithms in terms of localisation accuracy, mobility, synchronisation and overhead Our results show that our Mid–perpendicular, Checkout DV–hop and Selective 3–Anchor DV–hop algorithms support robust and dynamic localisation in the context of our adaptive localisation protocol

https://hal.archives-ouvertes.fr/hal-01120257/document

An adaptive range-free localisation protocol in wireless sensor networks

In this paper, we show how to verify computation tree logic (CTL) properties, using symbolic methods, on systems described in Promela. Symbolic representation is based on data decision diagrams (DDDs) which are n-valued Shared Decision Trees designed to represent dynamic systems with integer domain variables. We describe principal components used for the verification of Promela systems (DDD, representation of Promela programs with DDD, the transposition of the execution of Promela instructions into DDD). Then we compare and contrast our method with the model checker SPIN or classical binary decision diagram (BDD) techniques to highlight as to which system classes SPIN or our tool is more relevant.

/pdf/data-decision-diagrams-for-promela-systems-analysis-4hf279pkn2.pdf

Sami Taktak

Papers

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

A tool for automatic detection of deadlock in wormhole networks on chip

A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks

An adaptive range-free localisation protocol in wireless sensor networks

Data decision diagrams for Promela systems analysis