A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM. When a control signal is used in a buffer comprising a pull up and a pull down transistor, the input signal to the buffer is applied to the gate of the transistors in the control circuit. The two control signals are applied to the gates of the pull up and pull down transistors of the buffer to reduce transient current. In a further improvement, where the buffer includes a second inverter including a second pull up and a second pull down transistor, two feedback paths are employed to control the gates of the two transistors in the second inverter to control the slew rate of the buffer. The passing gate of the control circuit may be turned on or off by an enabling circuit so that if the circuit is implemented in an integrated circuit having input and output pins, the control circuit can be tri-stated so that an output pin may be used as an input pin when the passing gate is disabled.

Control circuit having outputs with differing rise and fall times

A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

Variable bitline precharge voltage sensing technique for DRAM structures

A sense amplifier of a semiconductor memory device for performing a high-speed sensing operation. A sensing node SAN and SAN of the sense amplifier is precharged to a power voltage level and during a sensing operation, first and second clock signals which are shifted to the power voltage and a ground voltage level, respectively, are applied to the sense amplifier. Thus, a potential difference of the sensing node dependent on a precharge state of the power voltage level is generated quickly and sufficiently. Therefore, the high speed sensing operation and a fast access of data can be performed, thereby improving the performance of the semiconductor memory device.

Sense amplifier for performing a high-speed sensing operation

An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.

Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations

A precharge circuit for use in a static random access memory is disclosed two step bit line pair precharging scheme in a precharge cycle performed prior to a read operation. The first precharging step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step is performed via means for precharging more dominantly than the transistor pair in response to a second pulse generated by the address transition detection circuit. Owing to the off-state of the N-channel MOS transistor pair in a read operation after a write operation, high speed read operation is obtained.

Sang K. Hwang

Papers

Precharge circuit for use in a semiconductor memory device