Patent
Precharge circuit for use in a semiconductor memory device
TLDR
In this article, a precharge circuit for static random access memory is described, where the first precharge step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step was performed via means for precharging more dominantly than the transistor pair in reaction to a second pulse generated via the address transition detection circuit.Abstract:
A precharge circuit for use in a static random access memory is disclosed two step bit line pair precharging scheme in a precharge cycle performed prior to a read operation. The first precharging step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step is performed via means for precharging more dominantly than the transistor pair in response to a second pulse generated by the address transition detection circuit. Owing to the off-state of the N-channel MOS transistor pair in a read operation after a write operation, high speed read operation is obtained.read more
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References
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Patent
Sense amplifier circuit
Takashi Obara,Shouji Kaneko +1 more
TL;DR: In this article, a sense amplifier circuit comprising a balancing circuit capable of establishing an electrical path between not only the sense nodes but also the control nodes which are operable to control transistors provided between the senses and a voltage supply to apply the supply voltage level to one sense node and remain low level on the other sense node for preparation of reading out of accessed information is provided.