A network adapter for a synchronous logical ring network operates on existing physical twisted-pair telephone topologies. Information propagates around the logical ring, reaching every device on each revolution around the network. Network devices are full-duplex, transmitting and receiving information on every clock cycle. Network devices arbitrate to be elected the network clock device. By synchronizing all network devices to a single reference clock, and providing fixed frames of information propagating around the network at consistent time intervals, the logical ring network ensures that information propagates from one device to another at consistent time intervals. The fixed-length frames are divided into two independent streams: a data stream for the distribution of real-time continuous digital media streams; and a system command stream for the distribution of system commands.

Synchronous network for digital media streams

In general, the invention features methods by which more than one client program connected to a network stores the same data item on a storage device of a data repository connected to the network. In one aspect, the method comprises encrypting the data item using a key derived from the content of the data item, determining a digital fingerprint of the data item, and storing the data item on the storage device at a location or locations associated with the digital fingerprint. In a second aspect, the method comprises determining a digital fingerprint of the data item, testing for whether the data item is already stored in the repository by comparing the digital fingerprint of the data item to the digital fingerprints of data items already in storage in the repository, and challenging a client that is attempting to deposit a data item already stored in the repository, to ascertain that the client has the full data item.

Data repository and method for promoting network storage of data

The present invention is directed to a method and system for disaggregating and connecting A/V components, and communicating A/V content stream information. An A/V stream from a source device is packaged for transmission over an IP network to one or more output devices. A brick device enables the integration of legacy A/V systems into the network supported A/V system. The brick device operates to provide analog signal and IP protocol conversion, along with the synchronization of received A/V stream data packets. The rendering and play of the A/V stream content on multiple output devices is synchronized to overcome distortions and other network idiosyncrasy and to facilitate a pleasant user experience.

Method and system for disaggregating audio/visual components

A home network, in one embodiment including a home wiring system; a demarcation point unit in electrical communication with the home wiring system; and a home network module in electrical communication with the home wiring system. The home network module is adapted for connection to a home electronic device. The demarcation point unit passes data to and receives data from the home electronic device through the home network module.

Home network system and method

Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture. Additional inventive elements conveyed include: an architectural overview of a communications processor; a data path protocol support model for a communications processor; an exemplary network processor employed as the core packet processor for the communications processor; an exemplary rings-based SOC switch fabric architecture; and a variety of quality of support features.

Communications system using rings architecture

A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.

High speed single chip digital video network apparatus

A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.

Single chip network adapter apparatus

A high performance graphics applications controller having a core processor and a coprocessor to independently perform desired graphics functions is provided. The core processor and the coprocessor divides processing tasks to speed execution and to reduce the burden on the host CPU. A direct memory access (DMA) controller cooperates with the coprocessor to generate source and destination addresses and employs a unique set of commands to speed operation. The core processor employs a local CPU and data and address catches to locally perform desired graphics operations independently but in conjunction with the coprocessor. The present invention has particular application with smart terminals and wherever pixel oriented data is required.

High performance graphics applications controller

A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.

Switched network hub on a chip

The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.

Sanjay Desai

Papers

High speed single chip digital video network apparatus

Single chip network adapter apparatus

High performance graphics applications controller

Switched network hub on a chip

Multi-port network adapter