National Institute of Standards and Technology における超伝導研究及び生活

In this paper a compact FPGA architecture for the AES algorithm with 128-bitkey targeted for low-costembedded applications is presented. Encryption, decryption and key schedule are all implemented using small resources of only 222 Slices and 3 Block RAMs. This implementation easily fits in a low-costXilinx Spartan II XC2S30 FPGA. This implementation can encrypt and decrypt data streams of 150 Mbps, which satisfies the needs of most embedded applications, including wireless communication. Specific features of Spartan II FPGAs enabling compact logic implementation are explored, and a new way of implementing MixColumnsand InvMixColumnstransformations using shared logic resources is presented.

/pdf/very-compact-fpga-implementation-of-the-aes-algorithm-w2e6txb66o.pdf

Very Compact FPGA Implementation of the AES Algorithm

The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD tools

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor This platform has been implemented on Xilinx Virtex IItm and Virtex II Protm devices The platform’s hardware architecture has been designed to be lightweight Two APIs (Application Program Interface) are described which abstract the low level configuration interface The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources It also provides support for relocatable partial bitstreams The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry

/pdf/a-self-reconfiguring-platform-47bh68r3yq.pdf

A Self-reconfiguring Platform

Summary form only given. The handling of an increasing number of automotive comfort functionalities has become a significant problem for the most automobile manufacturers since communication, power consumption, available space and cost become important issues for a growing number of engine control units. Our contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function multiplex.

An FPGA run-time system for dynamical on-demand reconfiguration

This paper presents a lightweight approach for embedded reconfiguration of Xilinx Virtex II/spl trade/ series FPGAs. A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array. The system provides a highly integrated, lightweight approach to dynamic reconfiguration for embedded systems. It combines the benefits of intelligent control, fast reconfiguration and small overhead.

/pdf/a-lightweight-approach-for-embedded-reconfiguration-of-fpgas-5ax9uxp82a.pdf

A Lightweight Approach for Embedded Reconfiguration of FPGAs

A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Reconfiguration of a programmable logic device using internal control

Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.

Run-time reconfigurable testing of programmable logic devices

Much has been written about the design and performance advantages of partial Run-Time Reconfiguration (RTR) over the last decade While the results have been promising, commercial support for partial RTR has lagged Until the introduction of the Xilinx Virtex(tm) family of devices, no mainstream, commercial FPGA has provided support for this capability In this paper we describe JRTR, a software package which provides direct support for partial run-time reconfiguration Using a cache-based model, this implementation provides fast, simple support for partial run-time reconfiguration While the current implementation is on the Xilinx Virtex family of devices using the JBits tool suite, this approach may be applied to any SRAM-based FPGA that provides basic support for RTR

/pdf/partial-run-time-reconfiguration-using-jrtr-1sfpv82eex.pdf

Scott P. McMillan

Papers

A Self-reconfiguring Platform

A Lightweight Approach for Embedded Reconfiguration of FPGAs

Reconfiguration of a programmable logic device using internal control

Run-time reconfigurable testing of programmable logic devices

Partial Run-Time Reconfiguration Using JRTR