The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high voltage capability and avalanche energy capability, suitable for use in integrated circuits as well as for discrete devices are disclosed. The semiconductor diodes are diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the vertical cylindrical metal oxide semiconductor field effect devices, and one diode terminal as the common connection with the sources of the vertical cylindrical metal oxide semiconductor field effect devices. The method of manufacturing the vertical cylindrical metal oxide semiconductor field effect devices is disclosed. Various device terminations can be employed to complete the diode devices. Various embodiments are disclosed.

Vertical metal oxide silicon field effect semiconductor diodes

A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses and substantially planar step surfaces, and implanting a dopant species through the mask layer into a portion of the semiconductor layer adjacent to the termination of the pn junction. The semiconductor layer is annealed to activate at least a portion of the implanted dopant species to form the graded junction termination extension.

Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same

Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindrical field effect devices are disclosed to exemplify the use of the pedestals and/or sidewalls. A system for forming the pedestals and sidewalls is described.

Sidewalls as semiconductor etch stop and diffusion barrier

Trench MOSFETs and self aligned processes for fabricating trench MOSFETs. These processes produce a higher density of trenches per unit area than can be obtained using prior art masking techniques. The invention self aligns all processing steps (implants, etches, depositions, etc.) to a single mask, thus reducing the pitch of the trenches by the added distances required for multiple masking photolithographic tolerances. The invention also places the source regions and contacts within the side walls of the trenches, thus eliminating the lateral dimensions required, for masking and source depositions or implants from the top surface, from the pitch of the trenches. Various embodiments are disclosed.

MOSFET power transistors and methods

A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On-resistance of P-channel RESURF (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at = gs V V 0 . 5 − , the specific on-resistance of the LDMOS with the tapered field oxide is about 2 5 . 31 cm m ⋅ Ω , while that of the LDMOS

Characteristics of p-channel SOI LDMOS Transistor with Tapered Field Oxides

The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO/sub 2/ implant mask. The p/sup +/-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p/sup +/-p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V. >

Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO 2 implant mask

A new Field Plate (FP) structure with taper oxide and shallow low doping region at the p-n junction edge, is proposed. The proposed structure relaxes the electric field crowding effect at the p-n junction of the FP structure by performing the high energy and low dose implantation through the taper SiO/sub 2/ implant mask. The fabricated p/sup +/-n diodes with the taper oxide and lightly doped junction extension structure, have a breakdown voltage of 500 V while the breakdown voltage of the conventional FP structure is 280 V. Also, numerical simulation shows that the termination area of the proposed structure is the 70% of that of the field limiting ring structure.

Seok-Nam Yoon

Papers

Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO 2 implant mask

A lightly doped shallow junction extension for the high breakdown voltage by double diffusion process using the taper SiO/sub 2/ mask