In this paper, insulated gate bipolar transistor (IGBT) models published in the literature are reviewed, analyzed, compared and classified into different categories according to mathematical type, objectives, complexity, accuracy and speed. Features of the different models are listed. Different modeling criteria are discussed according to various circuit conditions, structures, thermal considerations and accuracies. Some problems and trends in IGBT modeling are discussed.

A review of IGBT models

The current status of research in the field of power semiconductor device models is reviewed. For this purpose, the basic modeling problems and research issues, which have to be overcome in this field, are discussed. Some new and quite promising modeling concepts have been proposed, which are compared with more traditional ways of achieving an efficient tradeoff between the necessary accuracy, required simulation speed, and feasibility of parameter determination. From this comparison, a prediction of the future evolution of circuit simulation models for power semiconductor devices naturally emerges. Many of the different concepts are expected to survive only in an application niche, where their specific points of strength are important. However, three modeling concepts have already been proven to be successfully applicable to the complete spectrum of power semiconductor devices and have their strength for different grades of complexity of the power circuit. A revolutionary development from anticipated or long-due breakthroughs is on the other hand not expected in the foreseeable future.

Status and trends of power semiconductor device models for circuit simulation

A lateral thin-film Silicon-On-Insulator (SOI) JFET device includes a semiconductor substrate, a buried insulating on the substrate, and a JFET device in a thin semiconductor layer of a first conductivity type on the buried insulating layer. The device includes a source region of the first conductivity type, a control region of a second conductivity type which is laterally spaced apart from the source region and a lateral drift region of the first conductivity type adjacent to the control region. A drain region of the first conductivity type is provided laterally spaced apart from the control region in a first lateral direction by the lateral drift region, and at least one field plate electrode is provided over at least a major portion of the lateral drift region and is insulated from the drift region by an insulation region. The control region includes control region segments which are spaced apart in a second lateral direction perpendicular to the first lateral direction by portions of the thin semiconductor layer, thus providing a normally 'on' JFET device.

Lateral thin-film silicon-on-insulator (soi) jfet device

A first-order behavioral IGBT/gate drive model is proposed together with a procedure for deriving all model parameters. Despite the simplicity of the proposed model, comparison of model predictions with hardware measurements demonstrate the model to be accurate in predicting turn-on and turn-off transients.

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Behavioral IGBT modeling for predicting high frequency effects in motor drives

The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high voltage capability and avalanche energy capability, suitable for use in integrated circuits as well as for discrete devices are disclosed. The semiconductor diodes are diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the vertical cylindrical metal oxide semiconductor field effect devices, and one diode terminal as the common connection with the sources of the vertical cylindrical metal oxide semiconductor field effect devices. The method of manufacturing the vertical cylindrical metal oxide semiconductor field effect devices is disclosed. Various device terminations can be employed to complete the diode devices. Various embodiments are disclosed.

Vertical metal oxide silicon field effect semiconductor diodes

The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO/sub 2/ implant mask. The p/sup +/-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p/sup +/-p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V. >

Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO 2 implant mask

An accurate on-resistance model of VDMOS devices in the low voltage regimes is proposed and verified by numerical simulation results. The model considers the lateral Gaussian doping profiles in the channel region and exact current spreading angles in the epitaxial layer for both linear and cellular geometries by employing the conformal mapping. Results of the proposed model are in good agreement with those of 2D and quasi-3D simulations obtained by PISCES-IIB for a VDMOS device with 100 V rating. The on-resistance of a low voltage VDMOS may be considerably overestimated if it is analyzed by the conventional method.

An accurate on-resistance model for low voltage VDMOS devices

Analytical expressions are derived for the three-dimensional effect on the breakdown voltage of the planar junctions, which have the finite lateral radius of window curvature, by employing the suitable approximations for the electric field. The analytical results for nonpunchthrough and punchthrough cases are in excellent agreement with the results of the quasi-three-dimensional device simulation by MEDICI. For nonpunchthrough case, the critical electric fields at breakdown and the breakdown voltages are expressed successfully in a form which is normalized to the parallel plane case. Also, the breakdown voltages in punchthrough case are given in terms of the punchthrough voltage and the parallel plane breakdown voltage of p/sup +/-i-n/sup +/ diodes including the lateral radius of window curvature. The results may be applicable to the estimation of breakdown voltages in many practical power devices. >

Analytical expressions for the three-dimensional effect on the breakdown voltages of planar junctions in nonpunchthrough and punchthrough cases

The static and dynamic models of IGBT for the SPICE simulation have been successfully developed. The various circuit model parameters are extracted from the I-V and C-V characteristics of IGBT and implemented into our model. The SPICE simulation employing new model results agree well with the experimental values.

Parameter Extraction for the Static and Dynamic Model of IGBT

A new Field Plate (FP) structure with taper oxide and shallow low doping region at the p-n junction edge, is proposed. The proposed structure relaxes the electric field crowding effect at the p-n junction of the FP structure by performing the high energy and low dose implantation through the taper SiO/sub 2/ implant mask. The fabricated p/sup +/-n diodes with the taper oxide and lightly doped junction extension structure, have a breakdown voltage of 500 V while the breakdown voltage of the conventional FP structure is 280 V. Also, numerical simulation shows that the termination area of the proposed structure is the 70% of that of the field limiting ring structure.

Seong-Dong Kim

Papers

Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO 2 implant mask

An accurate on-resistance model for low voltage VDMOS devices

Analytical expressions for the three-dimensional effect on the breakdown voltages of planar junctions in nonpunchthrough and punchthrough cases

Parameter Extraction for the Static and Dynamic Model of IGBT

A lightly doped shallow junction extension for the high breakdown voltage by double diffusion process using the taper SiO/sub 2/ mask