In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters—low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance-induced by TSV stress.

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Experimental evidence is presented for silicon bandgap narrowing in uniaxially strained MOSFETs subjected to both tensile and compressive stress. For both n-channel MOSFETs with n+ polysilicon gate and p-channel MOSFETs with p+ polysilicon gate, the strain-induced threshold voltage shift (ΔVth) can be explicitly approximated from the changes in silicon bandgap (ΔEg) and carrier mobility (Δμ). From the measurements of both ΔVth and Δμ associated with the strain e, a simple ΔEg model at low strain is found to exactly match a tight-binding band structure calculation, clearly indicating the presence of uniaxial strain-induced silicon bandgap narrowing, regardless of strain or carrier type.

Evidence for Silicon Bandgap Narrowing in Uniaxially Strained MOSFETs Subjected to Tensile and Compressive Stress

In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.

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A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% – 9.05% and in 6T SRAM 2.51% – 4.76% and 3.77% – 5.64% decrease for storing 0 and 1 respectively.

A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors

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Effects of mechanical stress on the performance of metal-oxide-semiconductor transistors

This paper investigates the physics behind the overall on-current (Ion) improvement of n-channel metal-oxide-semiconductor (NMOS) transistors by uniaxial tensile stress. The strain-induced change in subthreshold off-current (Ioff) is related to the following strain-induced effects: (i) mobility enhancement, (ii) reduction in the saturation threshold voltage (Vth,sat), and (iii) improvement in subthreshold swing (Sts). By selecting transistors whose Ioff is less sensitive to the statistical variation in gate length, we studied the effects of process-induced tensile stress on Ion and Ioff of NMOS transistors. We found that both externally applied tensile stress and process-induced tensile stress led to a bigger percentage increase in subthreshold Ioff compared to the percentage increase in Ion. Our explanation is that the increase in Ioff is mainly due to an increase in mobility and a decrease in Vth,sat by tensile stress. The improvement of subthreshold swing by tensile stress can lead to a decrease in sub...

Seow Wei Lai

Papers

Mechanism for improvement of n-channel metal-oxide-semiconductor transistors by tensile stress