Ultrahigh-resolution displays for augmented reality (AR) and virtual reality (VR) applications require a novel architecture and process. Atomic-layer deposition (ALD) enables the facile fabrication of indium-gallium zinc oxide (IGZO) thin-film transistors (TFTs) on a substrate with a nonplanar surface due to its excellent step coverage and accurate thickness control. Here, we report all-ALD-derived TFTs using IGZO and HfO2 as the channel layer and gate insulator, respectively. A bilayer IGZO channel structure consisting of a 10 nm base layer (In0.52Ga0.29Zn0.19O) with good stability and a 3 nm boost layer (In0.82Ga0.08Zn0.10O) with extremely high mobility was designed based on a cation combinatorial study of the ALD-derived IGZO system. Reducing the thickness of the HfO2 dielectric film by the ALD process offers high areal capacitance in field-effect transistors, which allows low-voltage drivability and enhanced carrier transport. The intrinsic inferior stability of the HfO2 gate insulator was effectively mitigated by the insertion of an ALD-derived 4 nm Al2O3 interfacial layer between HfO2 and the IGZO film. The optimized bilayer IGZO TFTs with HfO2-based gate insulators exhibited excellent performances with a high field-effect mobility of 74.0 ± 0.91 cm2/(V s), a low subthreshold swing of 0.13 ± 0.01 V/dec, a threshold voltage of 0.20 ± 0.24 V, and an ION/OFF of ∼3.2 × 108 in a low-operation-voltage (≤2 V) range. This promising result was due to the synergic effects of a bilayer IGZO channel and HfO2-based gate insulator with a high permittivity, which were mainly attributed to the effective carrier confinement in the boost layer with high mobility, low free carrier density of the base layer with a low VO concentration, and HfO2-induced high effective capacitance.

Achieving a Low-Voltage, High-Mobility IGZO Transistor through an ALD-Derived Bilayer Channel and a Hafnia-Based Gate Dielectric Stack.

Low-temperature (≤400 °C), stackable oxide semiconductors are promising as an upper transistor ingredient for monolithic three-dimensional integration The atomic layer deposition (ALD) route provi

Atomic Layer Deposition Process-Enabled Carrier Mobility Boosting in Field-Effect Transistors through a Nanoscale ZnO/IGO Heterojunction

Theoretical and experimental studies of laser lift-off of nonwrinkled ultrathin polyimide film for flexible electronics

The effect of gallium (Ga) concentration on the structural evolution of atomic-layer-deposited indium gallium oxide (IGO) (In1-xGaxO) films as high-mobility n-channel semiconducting layers was investigated. Different Ga concentrations in 10-13 nm thick In1-xGaxO films allowed versatile phase structures to be amorphous, highly ordered, and randomly oriented crystalline by thermal annealing at either 400 or 700 °C for 1 h. Heavy Ga concentrations above 34 atom % caused a phase transformation from a polycrystalline bixbyite to an amorphous IGO film at 400 °C, while proper Ga concentration produced a highly ordered bixbyite crystal structure at 700 °C. The resulting highly ordered In0.66Ga0.34O film show unexpectedly high carrier mobility (μFE) values of 60.7 ± 1.0 cm2 V-1 s-1, a threshold voltage (VTH) of -0.80 ± 0.05 V, and an ION/OFF ratio of 5.1 × 109 in field-effect transistors (FETs). In contrast, the FETs having polycrystalline In1-xGaxO films with higher In fractions (x = 0.18 and 0.25) showed reasonable μFE values of 40.3 ± 1.6 and 31.5 ± 2.4 cm2 V-1 s-1, VTH of -0.64 ± 0.40 and -0.43 ± 0.06 V, and ION/OFF ratios of 2.5 × 109 and 1.4 × 109, respectively. The resulting superior performance of the In0.66Ga0.34O-film-based FET was attributed to a morphology having fewer grain boundaries, with higher mass densification and lower oxygen vacancy defect density of the bixbyite crystallites. Also, the In0.66Ga0.34O transistor was found to show the most stable behavior against an external gate bias stress.

High-Performance Thin-Film Transistors with an Atomic-Layer-Deposited Indium Gallium Oxide Channel: A Cation Combinatorial Approach.

Mechanically flexible vertical-channel-structured thin-film transistors (VTFTs) with a channel length of 200 nm were fabricated on 1.2 μm thick colorless polyimide (CPI) substrates. All layers comp...

Highly Robust Flexible Vertical-Channel Thin-Film Transistors Using Atomic-Layer-Deposited Oxide Channels and Zeocoat Spacers on Ultrathin Polyimide Substrates

Cationic compositional effects of amorphous In–Ga–Zn–O (a-IGZO) prepared by atomic layer deposition (ALD) were strategically investigated for thin film transistor applications. The atomic compositions (In : Ga : Zn) of ALD-IGZO films were varied to 1 : 1 : 1, 1 : 1 : 3, and 1 : 1 : 5 by controlling the ALD cyclic ratios. The relative content of oxygen vacancies and temperature-dependent electrical conductivities among the films markedly varied with the In/Zn ratio. The device employing the 1 : 1 : 5 composition exhibited inferior characteristics owing to the excessive Zn content in the IGZO channel. With increasing In/Zn ratio, the density of subgap states near both the conduction and valence bands increased, resulting in a higher degree of bias-stress instability. The device employing the 1 : 1 : 3 composition exhibited the most promising device characteristics including excellent stabilities under positive bias-stress at 60 °C and a negative bias-illumination-stress condition using a green wavelength, in which the threshold voltage shifts were estimated to be as low as +0.8 and −1.5 V, respectively.

Cationic compositional effects on the bias-stress stabilities of thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

We introduce mechanically flexible nonvolatile memory thin-film transistors (MTFTs) for future highly functional flexible and stretchable electronic devices and systems. The proposed memory devices are uniquely composed of oxide-semiconductor thin films and operated with charge-trap and detrap mechanisms for nonvolatile memory operations. Charge-trap-assisted MTFTs (CT-MTFTs) using In–Ga–Zn–O active and ZnO charge-trap layers are designed and fabricated on flexible poly(ethylene naphthalate) and colorless polyimide films prepared on carrier glass substrates. We describe the fabrication processes and evaluation methodologies for realizing flexible CT-MTFTs in a detailed way and discuss related technical issues. The device characteristics and memory performance of the fabricated flexible CT-MTFTs, including when the devices are mechanically strained, are extensively discussed. We also propose further improvements for remaining issues on device performance from the viewpoints of memory operations and mechanical flexibility.

https://iopscience.iop.org/article/10.7567/1347-4065/ab09e4/pdf

Charge-trap-assisted flexible nonvolatile memory applications using oxide-semiconductor thin-film transistors

Two-dimensional (2D) siloxene is attracting considerable research interest recently principally owing to its inherent compatibility with silicon-based semiconductor technology. -The synthesis of siloxene has been mostly limited to multilayered structures using traditional topochemical reaction procedures. Herein, we report high-yield synthesis of single to few-layer siloxene nanosheets by developing a two-step interlayer expansion and subsequent liquid phase exfoliation procedure. Our protocol enables high-yield production of few-layer siloxene nanosheets with a lateral dimension of up to 4 μm and thickness ranging from 0.8 to 4.8 nm, corresponding to single to a few layers, well stabilized in water. The atomically flat nature of exfoliated siloxene can be exploited for the construction of 2D/2D heterostructure membranes via typical solution processing. We demonstrate highly ordered graphene/siloxene heterostructure films with synergistic mechanical and electrical properties, which deliver noticeably high device capacitance when assembled into a coin cell symmetric supercapacitor device structures. Additionally, we demonstrate that the mechanically flexible exfoliated siloxene-graphene heterostructure enables its direct use in flexible and wearable supercapacitor applications.

Seung-Bo Ko

Papers

Cationic compositional effects on the bias-stress stabilities of thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

Charge-trap-assisted flexible nonvolatile memory applications using oxide-semiconductor thin-film transistors

Scalable Solution Phase Synthesis of 2D Siloxene via a Two-Step Interlayer Expansion Process.