When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.

On reducing peak current and power during test

In designs using DFT, such as scan, some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause nonfunctional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudofunctional.

On generating pseudo-functional delay fault tests for scan designs

This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

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At-speed scan test with low switching activity

Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and damage circuits under test. Several works have proposed methods to derive tests with lower peak and average switching activity during test response capture or during scan shifts. Some of these methods require additional hardware and modifications to the scan chains. This paper investigates a method to derive tests with reduced switching activity both during scan shifts and during test response captures. The method does not require additional hardware or modifications to the scan chains. The proposed method accepts a given test set and returns a test set of the same or smaller size with reduced switching activity. Experimental results on benchmark and industrial circuits are given

Low Shift and Capture Power Scan Tests

This paper proposes a method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS'89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.

Shaing-Jer Hsu

Papers

Test power reduction with multiple capture orders