Proceedings ArticleDOI
Test power reduction with multiple capture orders
Kuen-Jong Lee,Shaing-Jer Hsu,Chia-Ming Ho +2 more
- pp 26-31
Reads0
Chats0
TLDR
A multiple-capture-orders method is developed to guarantee the full scan fault coverage and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead.Abstract:
This paper proposes a method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS'89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.read more
Citations
More filters
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Proceedings ArticleDOI
On reducing peak current and power during test
TL;DR: Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.
Proceedings ArticleDOI
On generating pseudo-functional delay fault tests for scan designs
TL;DR: This work proposes new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states, which are essentially functional or pseudofunctional.
Proceedings ArticleDOI
At-speed scan test with low switching activity
TL;DR: A novel method to generate test vectors that mimic functional operation from switching activity point of view by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes is presented.
Proceedings ArticleDOI
Low Shift and Capture Power Scan Tests
TL;DR: This paper investigates a method to derive tests with reduced switching activity both during scan shifts and during test response captures that does not require additional hardware or modifications to the scan chains.
References
More filters
Proceedings ArticleDOI
Minimized power consumption for scan-based BIST
TL;DR: The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage.
Proceedings ArticleDOI
Adapting scan architectures for low power operation
TL;DR: A method of adapting conventional scan architectures such that they operate in a low power mode during test so that they maintain the test times of the pre-adapted scan architectures.
Journal ArticleDOI
Minimized Power Consumption for Scan-Based BIST
TL;DR: The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage.
Proceedings ArticleDOI
Two techniques for minimizing power dissipation in scan circuits during test application
S. Chakravarty,V.P. Dabholkar +1 more
TL;DR: Two techniques for reducing power dissipation during test application, when scan test structure is used, are proposed and are shown to be intractable.
Minimizing Power Dissipation in Scan Circuits During Test Application
TL;DR: In this paper, a scheme for reducing power dissipation during test application, when scan test structure is used, is proposed, and algorithms required to exploit the proposed technique are discussed.