During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss.

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing

Safety is one of the crucial features of autonomous drive platforms, and semiconductor chips used in these architectures must guarantee functional safety aspects mandated by ISO 26262 standard. To monitor the failures due to field defects, in-system-structural-tests are automatically run during key-on and/or key-off. Upon detection of any permanent defects by the in-system-test (IST) architecture, Drive platform responds to achieve the fail-safe state of the system. In this paper, we present the IST architecture that helps with achieving highest functional safety levels on the NVIDIA Drive platform.

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms

During wafer sort, the fabricated chips are subjected to tests that verify if they meet the design specification. Test application time plays a critical role while verifying large volume of dice in a given period of time. These tests are carried out on an automatic test equipment (ATE). The time spent on the ATE directly affects the final cost of the device. Hence it is paramount to reduce test application time such that the device can be verified reliably while keeping the test time to a minimum. While reducing test application time is important, power dissipation is also important while considering reduction in test time. Power dissipation is often a trade off when deciding the test frequency and becomes a major limiting factor. One of the major approaches to test time reduction during circuit design is to implement multiple scan chains. This approach reduces test time drastically when compared to a same device implemented using a single scan chain. Other approaches involve manipulating test hardware and test patterns to reduce test time and testing many dice in parallel. The objective of this thesis is to obtain an optimum solution to the trade off and the feasibility of such approaches which can lead to new test methods in hardware and software. The problem is approached in two ways (i) by scaling the supply voltage, and (ii) by scaling the test frequency. Additionally, the two methods can be combined to reduce test time further. These methods can be used in tandem with existing methods to provide additional gain in test time reduction. The proposed methodologies are verified by simulation and through experiments. The experiments were carried on the Advantest T2000GS ATE located at Auburn University, Alabama. The simulations were performed using ISCAS’89 benchmark circuits and results show up to 50% reduction in test time.

Reducing ATE Test Time by Voltage and Frequency Scaling

Power dissipated during test is a constraint when it comes to test time reduction. In this work, we show that for a given test the minimum test application time is achieved when the total energy is dissipated evenly at the rate of the maximum allowable power for the device under test. This result, the test time theorem, leads to two alternatives for reducing test time. In the first alternative, we scale the supply voltage down to reduce power, which in turn allows us to increase the clock frequency, of course within the limit imposed by the critical path. Thus, optimum voltage and frequency can be found to minimize the test time of a fixed frequency synchronous test. In the other alternative, which also benefits from the reduced voltage, the clock period is dynamically varied so that each cycle dissipates the maximum allowable power. This test, termed aperiodic clock test, according to the theorem achieves the lower bound on test time. An illustrative example of an ISCAS'89 benchmark circuit shows a test time reductionof 71 %.

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A Test Time Theorem and its Applications

A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.

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ATE test time reduction using asynchronous clock period

Excessive power dissipation caused by large amount of switching activities has been a major issue in scan-based testing. For large designs, the excessive switching activities during launch cycle can cause severe power droop, which cannot be recovered before capture cycle, rendering the at-speed scan testing more susceptible to the power droop. In this paper, we present a methodology to avoid power droop during scan capture without compromising at-speed test coverage. It is based on the use of a low area overhead hardware controller to control the clock gates. The methodology is ATPG (Automatic Test Pattern Generation)-independent, hence pattern generation time is not affected and pattern manipulation is not required. The effectiveness of this technique is demonstrated on several industrial designs.

A clock-gating based capture power droop reduction methodology for at-speed scan testing

Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on.

Debug apparatus and methods for dynamically switching power domains

MATHS (Mechanism to Access Test-Data over High-Speed Link) provides a high-throughput PCIe based system to structurally test system-on-chips (SOCs) at wafer and system-level. The system removes the need for expensive test equipment by eliminating the input/output pin (IO) requirements and memory per IO needs. It simplifies the ATE architecture and design to enable smaller form factors and reduce capital costs of ownership. MATHS enables eliminating the assembly test-insertion by directly testing the SOCs on system level platforms, further reducing the costs. Since the mechanism is based on PCIe standards, it is highly portable across all platforms including ATE, system-level test, board, and in-field testing.

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links

A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.

Chip debug during power gating events

It is realized that having a method/apparatus that accurately measures voltage noise is imperative for ATE and SLT testing to 1) reliably sign-off on production patterns; 2) effectively optimize low power settings of scan architecture; 3) screen for defects during ATE testing and apply structural patterns on SLT at desired Voltage/Frequency points; This requires optimized noise profiles and hence localized noise monitors for appropriate tuning. In addition, with NVIDIA’s chips foraying into the automotive space, functional safety has gained utmost priority, and the noise profile during In-System Test (IST) helps catch reliability and aging-related defects in the field that show up after stress and degradation. This paper proposes an enhancement to the in-system Noise Measurement macro (NMEAS) to record voltage noise during the application of structural DFT patterns, such as in ATE and SLT testing, which was not possible in the conventional noise measurement methods. The introduced technique utilizes a continuous free-running fast clock that feeds functional frequency to NMEAS during test which allows it to measure the voltage noise of the chip during both shift and capture phases. Also, a novel enable generation logic and a counter are introduced that allow for more precise characterization of the measured voltage noise data.

Shantanu Sarangi

Papers

A clock-gating based capture power droop reduction methodology for at-speed scan testing

Debug apparatus and methods for dynamically switching power domains

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links

Chip debug during power gating events

On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)