A new method to implement faster than quadratic convergence for Goldschmidt division using simple logic circuits is presented. While the approximate quotient converges quadratically in conventional Goldschmidt division, the new method achieves nearly cubic convergence. Although division with cubic convergence has been regarded as impractical due to its complexity, the proposed method reduces the logic complexity and the delay by using an approximate squarer with a simple logic implementation and a redundant binary Booth recoder. It is especially effective in a system that already has a radix-8 multiplier. As a result, the effective area for the reciprocal table can be reduced by 25.4%. The proposed method has been verified by SystemC and Verilog models. The final results are confirmed by simulation with both random double precision numbers and an exhaustive suite of 17-bit test vectors.

A Goldschmidt Division Method With Faster Than Quadratic Convergence

Efficient implementation of 3X for radix-8 encoding

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method.

Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma-Delta ADC

A novel dynamic latched comparator with reduced kickback noise for high-speed ADCs is presented. Dynamic latched comparators suffer from kickback noise. Especially the common-mode kickback noise becomes even more critical in applications with asymmetric input. By using common source input transistors and a decoupling mechanism the novel dynamic latched comparator produces much lower common-mode kickback noise, while the differential kickback noise is also significantly reduced. The simulated results show that the proposed comparator not only produces less than one third of the common-mode kickback noise of other typical dynamic latched comparators, but also settles faster.

Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs

A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed This converter works in PWM mode on heavy load condition In order to improve efficiency, it switches to PFM mode on light load condition With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 926% Simulated and implemented in CSMC 05 mum CMOS process

Design and implementation of high-efficiency and low-power DC-DC converter with PWM/PFM modes

This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated result of the proposed circuit in a 0.18 ?m standard CMOS technology show that, this comparator achieves low kick back noise to 0.2 mV, exhibits low power dissipation of 53 ?W at 1.8 V supply compared with conventional architectures at a very high speed operation of 250 MHz.

A low kick back noise latched comparator for high speed folding and interpolating ADC

A general approach is proposed for minimizing the chip area and minimizing the efficiency of the fully integrated CMOS continuous mode buck converters. It shows that most significant portion of the area is occupied by the passive component such as capacitors and inductors. Some design-oriented performance equations are proposed to show the key factors that determine the features of the converters in this paper. Chip size and conversion efficiency of buck converters are discussed to establish necessary guidelines for selecting parameters of converters. As an example, a monolithically integrated buck converter is designed based on a 0.5 mum CMOS technology. Simulation results indicate that the designed buck converter with minimized die size can deliver energy up to 450 mW at 3 V output under the condition of 5 V input. The converter efficiency is 76.8% at 80 MHz switching frequency

A new design strategy for the monolithic buck converters

A high-performance low power dissipation 32-bit floating point RISC microprocessor XJ-1 has been successfully fabricated in 0.35 /spl mu/m CMOS technology. A set of innovative optimization techniques are introduced for high performance operation, which include modified redundant Booth-3 algorithm for fast multiplication or division, dynamic SRAM mode control scheme for low power dissipation, embedded bus preselector improving the performance of bus interface, and the large capacity on-chip memory decreasing the amount of traffic with an external memory. These techniques improved the speed and quality with 38% boosted frequency and 39% reduced power dissipation. Each instruction and its random combinations have been tested, and the chip achieves 0.98 mA/MHz at 3.3 V power supply.

The research on optimization techniques of 32-bit floating-point RISC microprocessor

This paper presented a novel piecewise curvature-corrected technology,which can be accomplished in standard CMOS process technology without any extra masks for temperature compensation.Temperature coefficient is improved by ten Com- pared to the first order compensation.This novel curvature-correcting scheme can be used in almost any process technology yielding reliable temperature compensation.The additional circuitry required for this correction is compact and is easily implemented.In SMIC 0.18μm CMOS process,a precision piecewise curvature-corrected differential bandgap reference is designed.The simulation results show that differential reference is 1.9997V,total noise is 225nV,and PSRR is 98dB.Meantime,the precision piecewise cur- vature-corrected single-end bandgap reference implemented in CSMS 0.5μm process is embedded in a monolithic 100MHz PWM BUCK DC-DC converter as reference voltage.Experimental results show that reference voltage is 1.2501V,total noise is 670nV, PSRR is 66.7dB,and temperature coefficient is improved by six.Differential or single-end reference can be under 1V through changing parameters due to the current mode,which is adapted to low-voltage low-power portable devices.

The Design of Precision Piecewise Curvature-Corrected CMOS Bandgap Reference

A novel allocated-by-weight seed-based BIST (ASB) architecture has been proposed for combinational circuits to test A test sequence of ASB is termed as seeded weighted Gray cyclic shift sequence (SW-GCSS), generated by Gray cyclic shift sequence (GCSS) and canonical seeds GCSS, termed as the characteristic sequence is a single input change (SIC) sequence with transitions of its bits different from each other Based on theoretical deduction of the properties of canonical seeds, a novel algebraic model and an optimized algorithm have been developed, based on which a seed circuit is provided SW-GCSS whose vectors are unique should be assigned to CUT (Circuit Under Test) according to weights to improve test efficiency A method used to calculate and adjust weights is also given Experimental results on the ISCAS85 benchmark circuits show that ASB architecture can achieve a 593%∼973% power reduction compared with LFSRs, while ensuring high fault coverage, less test patterns and low hardware overhead

https://ieeexplore.ieee.org/iel5/6416128/6424977/06425064.pdf

Shao Zhibiao

Papers

A low kick back noise latched comparator for high speed folding and interpolating ADC

A new design strategy for the monolithic buck converters

The research on optimization techniques of 32-bit floating-point RISC microprocessor

The Design of Precision Piecewise Curvature-Corrected CMOS Bandgap Reference

A low power testing architecture for test-per-clock BIST