Proceedings ArticleDOI
A low kick back noise latched comparator for high speed folding and interpolating ADC
Qi Yu,Shao Zhibiao,Chen Ting,Zhang Guohe +3 more
- pp 1973-1976
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TLDR
In this article, an improved latched comparator which is suitable for high speed folding and interpolation ADC is presented. But the proposed comparator minimizes the kick back noise while regenerating the analog input signals.Abstract:
This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated result of the proposed circuit in a 0.18 ?m standard CMOS technology show that, this comparator achieves low kick back noise to 0.2 mV, exhibits low power dissipation of 53 ?W at 1.8 V supply compared with conventional architectures at a very high speed operation of 250 MHz.read more
Citations
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Journal ArticleDOI
Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma-Delta ADC
Mengyun Yue,Dong Wu,Zheyao Wang +2 more
TL;DR: The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method, and the advantages are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption.
Proceedings ArticleDOI
Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs
TL;DR: A novel dynamic latched comparator with reduced kickback noise for high-speed ADCs is presented by using common source input transistors and a decoupling mechanism, which produces much lower common-modeKickback noise, while the differential kickbacks noise is also significantly reduced.
Journal ArticleDOI
A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators
TL;DR: This work proposes a new delay equation for latch-based comparators that is based on Adomian decomposition method and gives more accurate delay characteristics compared with the conventional one.
Proceedings ArticleDOI
A capacitive dynamic comparator with low kickback noise for pipelined ADC
D. V. Duong,Thang Nguyen +1 more
TL;DR: In this article, a low kickback noise capacitive dynamic comparator is proposed, which is achieved by controlling additional MOSFETs in signal path to cancel voltage variation in the internal node of comparator.
Journal ArticleDOI
A 10-bit 100-MS/s CMOS pipelined folding A/D converter
TL;DR: In this article, a 10-bit 100-MSample/s analog-to-digital (A/D) converter with pipelined folding architecture is presented, which alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers.
References
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Journal ArticleDOI
The software radio architecture
TL;DR: A closer look at the canonical functional partitioning of channel coding into antenna, RF, IF, baseband, and bitstream segments and a brief treatment of the economics and likely future directions of software radio technology are provided.
Journal ArticleDOI
An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
TL;DR: An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology, resulting in a 75 MHz maximum full-scale input signal frequency.
Proceedings ArticleDOI
Low kickback noise techniques for CMOS latched comparators
P.M. Figueiredo,J.C. Vital +1 more
TL;DR: Current solutions to minimize the kickback noise in analog-to-digital converter architectures are reviewed and two new ones are proposed.
Proceedings ArticleDOI
An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs
TL;DR: Simulated results of the proposed circuit in a 0.35 /spl mu/m standard CMOS technology operating at supply voltages within the range of 1.0-1.5 V show that this comparator achieves low offset, reduced kickback noise, high mean-time to failure and exhibits low-power dissipation at very high-speed operation.
Proceedings ArticleDOI
A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters
TL;DR: A high-speed and high-resolution comparator intended to be implemented in a 12 bit 100 MHz pipeline analog-to-digital converter (ADC) for frequency wireless local area network application is proposed.