In order to simplify the management of the traditional network, software-defined networking (SDN) has been proposed as a promising paradigm shift that decouples control plane and data plane, providing programmability to configure the network. With the deployment and the applications of SDN, researchers have found that the controller placement directly affects network performance in SDN. In this paper, the state of the art of controller placement problem is surveyed from the perspective of optimization objective. First, we introduce the overview of SDN and controller placement problem. Then, we classify this paper of controller placement problem into four aspects (latency, reliability, and cost and multi-objective) depending on their objective and analyze specific algorithms in different application scenarios. Finally, we identify some relevant open issues and research challenge to deal with in the future and conclude the controller placement problem.

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A Survey of Controller Placement Problem in Software-Defined Networking

Flows of packets are dynamically mapped to resource queues. Flows of packets are received at a network device to be routed from the network device in a network. Each flow comprises packets to be sent from a source to a connection. Data is stored for a queue allocation table that maintains a plurality of buckets to which received packets for a flow are assigned and indicating which of a plurality of resource queues are allocated for respective buckets. For each packet in a flow, a hash function is computed from values in a header of the packet and the packet is assigned to one of the plurality of buckets based on the computed hash function. One of a plurality of resource queues is allocated for each bucket to which packets are assigned based on the computed hash function.

Dynamic load balancing without packet reordering

Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field.

Survey on Real-Time Networks-on-Chip

Software-Defined Networking (SDN) is a network paradigm introduced to overcome the inherent challenges of traditional networks. Its architecture is either deployed with a single controller or multiple controllers. While the first is not suitable for large-scale networks, the latter is confronted with a controller placement problem (CPP) in a large-scale network environment. CPP involves the challenge of deploying the optimal number of controllers within a network while meeting certain performance requirements considered conflicting in nature such as reliability, load balancing, latency, energy efficiency, and computation time. A single optimal or random placement may not be feasible in CPP and careful planning is of the essence to find an appropriate trade-off among the metrics. To achieve this, several CPP approaches have been proposed, developed, and deployed over the years, each having its unique objectives, strengths, and weaknesses. Therefore, this paper performed a comprehensive review of some of the existing approaches to identify the unique solutions offered, comprehend the different strategies and the challenges that exist as well as provide researchers with future directions aimed at improving the optimum location and allocation of controllers, in particular, for SDN application in wireless sensor network (WSN). The findings revealed several existing solutions and algorithms as well as several challenges such as the need for an efficient algorithm, attack-aware, cost-aware, and energy-aware CPP schemes while achieving a good quality of service.

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Comprehensive Review of SDN Controller Placement Strategies

The delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chips (NoCs). In the paper, we revisit two state-of-the-art analysis models for real-time communication in wormhole NoCs with priority-based preemptive arbitration and show that the models only support specific router architectures with large buffer sizes. We then propose an extended analysis model to estimate delay upper-bounds for all router architectures and buffer sizes by identifying and analyzing the differences between upstream and downstream indirect interferences according to the relative positions of traffic flows and taking the buffer influence into consideration. Simulated evaluations show that our model supports one more router architecture and applies to small buffer sizes compared to the previous models.

Extending Real-Time Analysis for Wormhole NoCs

We propose a circuit switching Network-on-chip with a parallel probe searching setup method, which can search the entire network in constant time, only dependent on the network size but independent of the network load. Under a specific search policy, the setup procedure is guaranteed to terminate in time 3D+6 cycles, where D is the geometric distance between source and destination. If a path can be found, the method succeeds in 3D+6 cycles; if a path cannot be found, it fails in maximum 3D+6 cycles. Compared to previous work, our method can reduce the setup time and enhance the success rate of setups. Our experiments show that compared with a sequential probe searching method, this method can reduce the search time by up to 20%. Compared with a centralized channel allocator method, this method can enhance the success rate by up to 20%.

Parallel probing: dynamic and constant time setup procedure in circuit switching NoC

We propose a Time-Division Multiplexing (TDM) based connection oriented NoC with a novel double time-wheel router architecture combined with a run-time parallel probing setup method. In comparison with traditional TDM connection setup methods, our design has the following advantages: (1) it allocates paths and time slots at run-time; (2) it is fast with predictable and bounded setup latency; (3) it avoids additional resources (no auxiliary network or central processor to find and manage connections); (4) it is fully distributed and therefore it scales nicely with network size. Compared to a packet based setup method, our probe based design can reduce path setup delay by 81% and increase network load by 110% in an 8×8 mesh, while avoiding the auxiliary network. Compared to a centralized method, our solution can double the success rate, while eliminating the central resource for path setup and reducing the wire overhead. Synthesis results suggest that our design is faster and smaller than all comparable solutions.

Parallel probe based dynamic connection setup in TDM NoCs

Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance. In this paper we designed a circuit switched NoC and compared that with packet switched NoC. By speculation and analysis, we propose that, as packet size increases, performance decreases for packet switched NoC, while it increases for circuit switched NoC. By close examination on the router architecture, we suggest that circuit switched NoC can operate at a higher clock frequency than packet switched NoC, and thus at zero load above a certain packet size circuit switched NoC could be better than packet switched NoC in packet delay. Experiment results support our intuitions and analysis. We find the cross-over point, above which circuit switching has lower latency, is around 30 flits/packet under low load and 60-70 flits/packet under high network load.

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC

For large-scale programmable networks, flexible deployment of distributed control planes is essential for service availability and performance However, existing approaches only focus on placing controllers whereas the consequent control traffic is often ignored In this paper, we propose a black-box optimization framework offering the additional steps for quanti-fying the effect of the consequent control traffic when deploying a distributed control plane Evaluating different implementations of the framework over real-world topologies shows that close to optimal solutions can be achieved Moreover, experiments indicate that running a method for controller placement without considering the control traffic, cause excessive bandwidth usage (worst cases varying between 201%-501% more) and congestion, compared to our approach

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Flexible distributed control plane deployment

TDM (Time Division Multiplexing) is a well-known technique to provide QoS guarantees in NoCs. However, unused time slots commonly exist in TDM NoCs. In the paper, we propose a TDM highway technique which can enhance the slot utilization of TDM NoCs. A TDM highway is an express TDM connection composed of special buffer queues, called highway channels (HWCs). It can enhance the throughput and reduce data transfer delay of the connection, while keeping the quality of service (QoS) guarantee on minimum bandwidth and in-order packet delivery. We have developed a dynamic and repetitive highway setup policy which has no dependency on particular TDM NoC techniques and no overhead on traffic flows. As a result, highways can be efficiently established and utilized in various TDM NoCs.According to our experiments, compared to a traditional TDM NoC, adding one HWC with two buffers to every input port of routers in an 8×8 mesh can reduce data delay by up to 80% and increase the maximum throughput by up to 310%. More improvements can be achieved by adding more HWCs per input per router, or more buffers per HWC. We also use a set of MPSoC application benchmarks to evaluate our highway technique. The experiment results suggest that with highway, we can reduce application run time up to 51%.

Shaoteng Liu

Papers

Parallel probing: dynamic and constant time setup procedure in circuit switching NoC

Parallel probe based dynamic connection setup in TDM NoCs

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC

Flexible distributed control plane deployment

Highway in TDM NoCs