Optimum wire sizing of RLC interconnect with repeaters

The threshold voltage (Vth) of a FinFET device varies between the on and off mode: Vth is lower when the transistor is on and it is higher when the transistor is off Such a property is ideal for low-power designs with low supply voltage (Vdd) The low Vth provides high circuit speed even when Vdd is low, while the high standby Vth effectively controls the leakage In this work, we exploit this property to achieve both high-speed and low-power operations First, we develop an equivalent sub-circuit model of a FinFET transistor for design explorations The accuracy of this model is verified with TCAD simulations Then, we optimize key device parameters to obtain a large range of Vth between dynamic and standby mode: a thicker gate oxide and a thinner silicon body are desirable for this low-power design Using the optimized FinFET device at 32nm node, we demonstrate that more than 35% reduction in total energy can be achieved without sacrificing the speed We further benchmark the performance of representative logic and memory units under process variations

Optimizing finfet technology for high-speed and low-power design

Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive which can affect signal behavior in long interconnects. The line inductance should, therefore, be considered in determining the optimum number and size of the repeaters driving a line. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by repeaters. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low power design objectives. A reduction in power of 65% and delay of 97% is achieved for an example repeater system.

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. A 2π RLC interconnect model is used to investigate the effects of both coupling capacitance and mutual inductance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.

Shielding Methodologies in the Presence of Power/Ground Noise

In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on the characteristics of the 10 nm driver circuit. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, the impact of the BEOL on the circuit performance can be determined. The interconnect delay is plotted as a function of wire resistance, via resistance and capacitance. In order to better optimize the BEOL architecture, contour plots of resistance versus capacitance are presented in this paper. The result of this paper is indicating a strong dependency of circuit performance on the wiring length which is a new challenge. Optimization of BEOL architecture therefore requires a new approach which is outlined in this paper. As a result, we would like to bring this to the design community's attention.

Interconnect performance and scaling strategy at the 5 nm Node

Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.

Shen Lin

Papers

RLC signal integrity analysis of high-speed global interconnects [CMOS]