A semiconductor chip having a P− substrate and an N+ epitaxial layer grown on the P− substrate is shown. A P− circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.

Moat construction to reduce noise coupling to a quiet supply

The disclosure provides a structure for a microelectromechanical system (MEMS)-based resonator device. The structure for the MEMS-based resonator device includes at least one resonator unit. The at least one resonator unit comprises a substrate having a trench therein. A pair of first electrodes is disposed on a pair of sidewalls of the trench. A piezoelectric material fills the trench, covering the pair of first electrodes. A second electrode is embedded in the piezoelectric material, separated from the pair of first electrodes by the piezoelectric material. The second electrode disposed in the trench is parallel to the pair of first electrodes.

Microelectromechanical system-based resonator device

The invention provides a fabrication method of a super-junction field-effect transistor. The fabrication method of the super-junction field-effect transistor comprises the steps of forming a terminal base structure on a surface of an N-type epitaxial layer, wherein the terminal base structure comprises a main junction region and an annular region, the annular region is arranged at the periphery of the main junction region, and a plurality of annular P-type posts are formed in the annular region; forming a silicon nitride layer on the surface of the N-type epitaxial layer, wherein the silicon nitride layer covers the main junction region and the plurality of annular P-type posts; etching the silicon nitride layer of the annular region to form a plurality of strip-shaped opening regions, wherein the strip-shaped opening regions are perpendicular to the annular P-type posts, a part of a region on a surface of the annular region is exposed by the strip-shaped openings; and oxidizing the surface of the annular region to form a plurality of strip-shaped silicon oxide layers on the plurality of annular opening regions, and removing the silicon nitride layer on the surface of the N-type epitaxial layer. With the method provided by the invention, the reliability and the pressure-resistant degradation capability of the device can be greatly.

Fabrication method of super-junction field-effect transistor

The invention discloses a hyperconjugation terminal structure of a longitudinal double-diffused metal-oxide field effect transistor, which comprises an N-type heavily-doped silicon substrate which is simultaneously used as a drain region, wherein a drain electrode metal is arranged on the lower surface of the N-type heavily-doped silicon substrate; an N-type doping silicon epitaxial layer is arranged on the upper surface of the N-type heavily-doped silicon substrate; a hyperconjugation structure is arranged on the N-type doping silicon epitaxial layer and comprises P-type doped silicon columnar regions and N-type doped silicon columnar regions which are arrayed alternatively; and a silicon dioxide layer is arranged on the hyperconjugation structure. The hyperconjugation terminal structureis characterized in that a row of N-type doped silicon regions are arranged at the top of the P-type doped silicon columnar regions; and a row of P-type doped silicon region are arranged at the top of the N-type doped silicon columnar regions.

Hyperconjugation terminal structure of longitudinal double-diffused metal-oxide field effect transistor

The invention relates to a semiconductor isolation structure. More particularly, the present invention relates to a semiconductor isolation structure suitable for providing high voltage isolation. Embodiments disclosed include a semiconductor structure (10) comprising: a first semiconductor region (R1), a second semiconductor region (R2) within the first semiconductor region (R1), and a voltage isolator (11) separating the first and second semiconductor regions (R1, R2), the voltage isolator (11) comprising: a nested series of insulating regions (T1, T2) around the perimeter of the second semiconductor region (R2), an intermediate semiconductor region (I1, I2) between each adjacent pair of nested insulating regions (T1, T2), and a voltage control device (12) comprising a conducting element (D1-D3) connected to at least one intermediate semiconductor region (I1, I2) in parallel with the at least one insulating region (T1, T2), so as to control a voltage across the at least one insulating region (T1, T2).

Semiconductor isolation structure

A high voltage isolation structure based on silicon on an insulator includes that a surface passivation layer is arranged on an N-type epitaxial layer in a silicon structure on the insulator, a high voltage circuit area, a multi-deep-groove isolation structure and a low voltage circuit area are arranged in the N-type epitaxial layer, the high voltage circuit area is enclosed by the multi-deep-groove isolation structure, and the multi-deep-groove isolation structure is composed of 2 to 20 deep groove isolation structures. The high voltage isolation structure is characterized in that a high-resistance polycrystalline silicon field plate is arranged on the surface passivation layer, the N-type epitaxial layer of the high voltage circuit area and the low voltage circuit area is electrically connected with electrode contact holes, and the N-type epitaxial layer between every adjacent deep groove isolation structures is electrically connected with middle electrode contact holes. Two ends of the high-resistance polycrystalline silicon field plate are respectively electrically connected with the electrode contact holes in the high voltage circuit area and the low voltage circuit area, and the high-resistance polycrystalline silicon field plate is sequentially electrically connected with each electrode contact hole from inside to outside.

High voltage isolation structure based on silicon on insulator

A terminal structure of a superjunction VDMOS with a discontinuous surface field oxidation layer is disclosed. The structure comprises an annular N-type heavy doping silicon substrate which is used as a drain region. An inner border and an outer border of the N-type heavy doping silicon substrate are in a rectangle shape. A drain electrode metal is arranged on a lower surface of the N-type heavy doping silicon substrate. An N-type doping silicon extension layer is arranged on an upper surface of the N-type heavy doping silicon substrate. A superjunction structure is arranged on the N-type doping silicon extension layer. The superjunction structure comprises: P-type doping-silicon columnar areas and N-type doping-silicon columnar areas. And the P-type doping-silicon columnar areas and the N-type doping-silicon columnar areas are vertically alternatively arranged along the terminal structure. The terminal structure is characterized in that: a silica area and bar-shaped silica are arranged on the superjunction structure; the bar-shaped silica is positioned on a longitudinal side of the terminal structure and is vertically parallelly arranged along the terminal structure; the silica area covers a lateral side of the terminal structure.

Terminal structure of superjunction VDMOS with discontinuous surface field oxidation layer

The utility model provides a terminal structure of a super junction VDMOS. The terminal structure of the super junction VDMOS includes an N-type heavy doping silicon substrate that also functions as a drain region. A drain electrode metal is arranged on the lower surface of the N-type heavy doping silicon substrate. An N-type doping silicon epitaxial layer is arranged on the upper surface of the N-type heavy doping silicon substrate. A super junction structure is arranged on the N-type doping silicon epitaxial layer. The super junction structure includes a P-type doping silicon columnar area and an N-type doping silicon columnar area. The P-type doping silicon columnar area and the N-type doping silicon columnar area are arranged alternately in a staggered pattern. A silica layer is arranged on the super junction structure. It is characterized in that a row of N-type doping silicon areas is arranged on the top of the P-type doping silicon columnar area while a row of P-type doping silicon areas is arranged on the top of the N-type doping silicon columnar area.

Shengli Lu

Papers

High voltage isolation structure based on silicon on insulator

Terminal structure of superjunction VDMOS with discontinuous surface field oxidation layer

Terminal structure of super junction VDMOS

Hyperconjugation terminal structure of longitudinal double-diffused metal-oxide field effect transistor