Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and self-organizing semiconductors. We show that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers. High mobilities of 0.02 square centimeters per volt second and on-off current switching ratios of 10 5 were achieved.

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High-Resolution Inkjet Printing of All-Polymer Transistor Circuits

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

http://science.sciencemag.org/content/sci/311/5758/208.full.pdf

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

The present invention provides methods, systems and system components for transferring, assembling and integrating features and arrays of features having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods of the present invention utilize principles of ‘soft adhesion’ to guide the transfer, assembly and/or integration of features, such as printable semiconductor elements or other components of electronic devices. Methods of the present invention are useful for transferring features from a donor substrate to the transfer surface of an elastomeric transfer device and, optionally, from the transfer surface of an elastomeric transfer device to the receiving surface of a receiving substrate. The present methods and systems provide highly efficient, registered transfer of features and arrays of features, such as printable semiconductor element, in a concerted manner that maintains the relative spatial orientations of transferred features.

Pattern Transfer Printing by Kinetic Control of Adhesion to an Elastomeric Stamp

The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates

Ultrathin films of single-walled carbon nanotubes (SWNTs) represent an attractive, emerging class of material, with properties that can approach the exceptional electrical, mechanical, and optical characteristics of individual SWNTs, in a format that, unlike isolated tubes, is readily suitable for scalable integration into devices. These features suggest the potential for realistic applications as conducting or semiconducting layers in diverse types of electronic, optoelectronic and sensor systems. This article reviews recent advances in assembly techniques for forming such films, modeling and experimental work that reveals their collective properties, and engineering aspects of implementation in sensors and in electronic devices and circuits with various levels of complexity. A concluding discussion provides some perspectives on possibilities for future work in fundamental and applied aspects.

http://www.ifc.dicp.ac.cn/library/cailiao/pdf1/11.pdf

Ultrathin Films of Single-Walled Carbon Nanotubes for Electronics and Sensors: A Review of Fundamental and Applied Aspects

The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

The effect of NH3 plasma treatment of the hydrogenated amorphous silicon nitride (a‐SiNx:H) gate insulator on the performance of hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors (TFTs) has been studied for different deposition conditions of the gate nitride. The TFT subthreshold slope and threshold voltage decrease with increasing rf power of gate nitride deposition. When increasing the rf power from 25 to 100 W, an increase in field‐effect mobility, from 0.29 to 0.37 cm2/V s, is obtained. The NH3 plasma treatment causes a general increase in subthreshold slope and threshold voltage. It also degrades the field‐effect mobility as large as 40%. However, the desirable effect of the plasma treatment is that the resulting devices have a higher stability exhibited by a 25% reduction of hysteresis width of transfer characteristics and by their higher resistance to prolonged positive gate field application. Based only on the electrical measurements, an exact model of the plasma interaction with the a...

Effect of NH3 plasma treatment of gate nitride on the performance of amorphous silicon thin‐film transistors

The turn-on transient behavior of amorphous-silicon (a-Si:H) thin-film transistors (TFT) was measured. The source current decay, after the initial step, had a double exponential decay within the first 6 ms. The source-current decay rate did not depend on the drain voltage, gate voltage or geometry of the device. In this study a modeling methodology based on a table look-up procedure was used to simulate the turn-on transient behavior of the a-Si:H TFT. Based on experimental evidence, the original five look-up tables were simplified to two tables. The simplified set of two tables was used to simulate the long-term transient behavior and yielded good agreement with the experimental results.

Simulation of the turn-on transient behavior of amorphous-silicon thin-film transistors

The inter-electrode capacitance-voltage (C-V) characteristics of amorphous silicon (a-Si:H) thin film transistor (TFT) were modeled and measured. The gate or induced channel charge was derived on the basis of the parameters and basic expressions of the static I-V model, which was developed by employing the simpified CFO energy band model and the simplified Davis-Mott energy band model. Analytical expressions for the C-V characteristics of an a-Si:H MIS capacitor were derived and applied to obtain an inter-electrode C-V model of an a-Si:H TFT. For this C-V model, the complicated calculations of the field-dependent mobility is not necessary. The simplified trapping/detrapping mechanism and the frequency variations of the measured capacitances are incorporated. The calculated data were illustrated along with the experimental results.

Shengwen Luan

Papers

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

Effect of NH3 plasma treatment of gate nitride on the performance of amorphous silicon thin‐film transistors

Simulation of the turn-on transient behavior of amorphous-silicon thin-film transistors

A computer model for inter-electrode capacitance-voltage characteristics of an a-Si:H TFT