An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material

High-performance cmos soi device on hybrid crystal-oriented substrates

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

High performance stress-enhanced mosfets using si:c and sige epitaxial source/drain and method of manufacture

The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN

A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.

Manufacture system for semiconductor device with thin gate insulating film

A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

Strained finfet cmos device structures

A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N 2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO 2 interface than either N 2 O oxynitride or nitridation of SiO 2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N 2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.

Shi-Chung Sun

Papers

Gate dielectric based on oxynitride grown in N2 O and annealed in NO