Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top of the flag)’ formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applications. The division methodology was implemented through half of the divisor bit instead of the actual divisor, subtraction and little multiplication. Propagation delay and dynamic power consumption of divider circuitry were minimised significantly by stage reduction through Vedic division methodology. The functionality of the division algorithm was checked and performance parameters like propagation delay and dynamic power consumption were calculated through spice spectre with 90 nm complementary metal oxide semiconductor technology. The propagation delay of the resulted (32 ÷ 16) bit divider circuitry was only ∼300 ns and consumed ∼32.5 mW power for a layout area of 17.39 mm2. Combination of Boolean arithmetic along with ancient Vedic mathematics, substantial amount of iterations were reduced resulted as ∼47, ∼38, 34% reduction in delay and ∼34, ∼21, ∼18% reduction in power were investigated compared with the mostly used (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) architectures.

Vedic division methodology for high-speed very large scale integration applications

In this paper, the design of high performance digital divider based on ancient Indian Vedic mathematics technique is presented. A Vedic mathematics technique called the Parāvartya Yojayet ("Transpose and Apply") is applied to obtain the high performance by reducing the propagation delay, area consumption with minimum electric power consumption. The operation of the digital divider division and other performance parameters like propagation delay and electric power consumption were calculated through Xilinx ISE 14.4 Spartan-6 FPGA with 45 nm low-power copper process technology that delivers the best balance of performance, cost, & power. The delay of the obtained 8 ÷4 bit and 16 ÷ 8 bit digital divider was only ~ 4.91 ns (with 0.08 ns slack) & ~ 5.851ns (with 0.02 ns slack), consumed ~1.3586 mW & ~1.73 mW electric power for a LUT utilization of 0.63% & 5% respectively. Computation using Vedic mathematics decreases considerable extent of iterations resulted in minimized delay and power compared to the mostly used non – Vedic (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) & Vedic architectures.

Design Of High Performance Digital Divider

Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is challenged by the interaction between tasks in shared resources, which impacts tasks’ energy consumption in uncontrolled ways. Some accurate mechanisms have been devised recently to estimate per-task energy consumed on-chip in multicores, but there is a lack of such mechanisms for DRAM memories. This article makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations. In particular, the contributions of this article are (i) an ideal per-task energy metering model for DRAM memories; (ii) DReAM, an accurate yet low cost implementation of the ideal model (less than 5% accuracy error when 16 tasks share memory); and (iii) a comparison with standard methods (even distribution and access-count based) proving that DReAM is much more accurate than these other methods.

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DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems

Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root.

Formal verification of bit-serial division and bit-serial square-root circuit designs

Chip multi-core processors (CMPs) are the preferred processing platform across different domains such as data centers, real-time systems and mobile devices. In all those domains, energy is arguably the most expensive resource in a computing system, in particular, with fastest growth. Therefore, measuring the energy usage draws vast attention. Current studies mostly focus on obtaining finer-granularity energy measurement, such as measuring power in smaller time intervals, distributing energy to hardware components or software components. Such studies focus on scenarios where system energy is measured under the assumption that only one program is running in the system. So far, there is no hardware-level mechanism proposed to distribute the system energy to multiple running programs in a resource sharing multi-core system in an exact way.
For the first time, we have formalized the need for per-task energy measurement in multicore by establishing a two-fold concept: Per-Task Energy Metering (PTEM) and Sensible Energy Accounting (SEA). In the scenario where many tasks running in parallel in a multicore system: For each task, the target of PTEM is to provide estimate of the actual energy consumption at runtime based on its resource usage during execution; and SEA aims at providing estimates on the energy it would have consumed when running in isolation with a particular fraction of system's resources.
Accurately determining the energy consumed by each task in a system will become of prominent importance in future multi-core based systems as it offers several benefits including (i) Selection of appropriate co-runners, (ii) improved energy-aware task scheduling and (iii) energy-aware billing in data centers.
We have shown how these two concepts can be applied to the main components of a computing system: the processor and the memory system. At first, we have applied PTEM to the processor by means of tracking the activities and occupancy of all the resources in a per-task basis. Secondly, we have applied PTEM to the memory system by means of tracking the activities and the state switches of memory banks. Then, we have applied SEA to the processor by predicting the activities and execution time for each task when they run with an fraction of chip resources alone. And last, we apply SEA to the memory system, by means of predicting activities, execution time and the time invoking memory system for each task. As for all these works, by trading-off the hardware cost with the estimation accuracy, we have obtained the implementable and affordable cost mechanisms with high accuracy.
We have also shown how these techniques can be applied in different scenarios, such as, to detect significant energy usage variations for any particular task and to develop more energy efficient scheduling policy for the multi-core system.
These works in this thesis have been published into IEEE/ACM journals and conferences proceedings that can be found in the publication chapter of this thesis.

Per-task energy metering and accounting in the multicore era

In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient generation, our method makes use of the magnitude difference between the partial dividend and the divisor for the next iteration so that the proper weight of the quotient can be obtained more rapidly than the conventional methods. Our proposed architecture is very simple compared to the multiplication-based methods such as those that are based on Newton-Raphson. Simulation results show that our proposed method can achieve less than half the number of iterations required by the conventional division (i.e. less than nil vs. n, where n is the bit-width of the dividend and the divisor). The proposed architecture has been synthesized in 0.13 mum CMOS standard cell library to demonstrate the delay and the power efficiency.

Shin-Mao Li

Papers

A novel VLSI iterative divider architecture for fast quotient generation