A circuit module that contains a planar array of chips has an improved fin assembly that transfers heat to a liquid coolant that is circulated through the fins in a single pass so that there is a tendency for the upstream edge of the fins to run cold and the downstream edge to run hot. The module can be immersed in the coolant. A shroud on the fins confines the coolant flow to channels defined by the fins, the shroud, and the base of the fins. The fin assembly is constructed so that the coolant channels are narrowed as a function of the temperature of the liquid coolant. The narrowing channels increase the coolant velocity and thereby improves the heat transfer at what would otherwise become the hot end of the module. The coolant velocity is increased at the appropriate rate to maintain equal cooling along the direction of coolant flow. The narrowing channels can be combined with other techniques for improving heat transfer, and in one embodiment the fin assembly has sets of fins spaced that increase in density along the direction of coolant flow. The increased fin density constricts the channels and thereby increases the coolant velocity. Modules with this fin assembly can be stacked closely together in an enclosure for a processing component. The processing component can hold other heat producing circuit devices either downstream of the finned modules or in a parallel coolant path.

Immersion cooled circuit module with improved fins

The state-of-the-art in air- and liquid-cooled multichip modules is examined. An effort is made to identify the salient features of eight distinct modules, define their thermal characteristics, and establish a consistent basis for comparing and evaluating their thermal performance.

Thermal Management of Air- and Liquid-Cooled Multichip Modules

The model presented in this work is based on an extension of the constant angle heat spreading, taking into account chip and substrate dimensions, and changing the spreading angle accordingly. This yields to closed form expressions accurate enough for most practical applications. Circular, square, and rectangular geometries have been analyzed and the results compared with Bessel and Fourier series-like solutions.

A closed form solution of junction to substrate thermal resistance in semiconductor chips

The integrated circuit device is modeled as a four-layer structure with multiple heat sources located on the surface of the first layer and with the fourth layer representing the device package. Each layer is assumed to have the same rectangular dimensions. Using the separation of variables, an analytical solution for the temperature at any location inside and on the boundaries of the structure is derived. Based upon the solution obtained, a computer program, Thermal, has been written in Fortran. Characteristics of the solution were studied, and several representative device structures were analyzed. The results of the simulation show how the device thermal resistance is affected by the die-bonding layer properties, the electrodes on the chip surface, and the heat spreader at the bottom surface of the chip. A FET power device was also analyzed to illustrate the very narrow hot zones produced on the chip surface, suggesting that the thermal measurement techniques must have adequate spatial resolution to measure the peak temperatures accurately. The lateral spread of heat flux into the regions of the package extending beyond the chip dimensions was studied using the boundary element method. An iteration technique based on the analytical solution has also been developed to account for the effect of this lateral heat spread. The corrected temperature using this iteration technique agrees to within 3.7% with that obtained using the boundary element method. >

Thermal analysis of integrated circuit devices and packages

It was thought that the invention of the transistor, with its relatively low power requirements, would greatly minimize, if not totally eliminate, all cooling concerns. Such thoughts, however, were short lived, as engineers sought to improve performance, cost, and reliability by packaging greater numbers of circuits in an ever-smaller space. In fact, power densities at the component level have increased dramatically over the years. In mainframe computers, chips may be found with power dissipations ranging between 20 and 40 W, and chips with power dissipation in excess of 10 W may be found in many PC and workstation applications. Considering one example from a mainframe computer, a 7 × 7-mm chip dissipating 30 W, results in a heat flux of more than 6 × 105 W/m2. As shown in Figure 4-1, this is only about two orders of magnitude less than that on the surface of the sun [1]. But the sun’s surface temperature is 6000°C, compared to a maximum operating temperature in the range of 100°C for a typical semiconductor chip.

Heat Transfer in Electronic Packages

The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descriptions of packages and results of studies are presented and discussed here.

Shin Nakao

Papers

High Thermal Conduction Package Technology for Flip Chip Devices