The recent combination of scanning electron microscopy and digital image correlation (SEM-DIC) enables the experimental investigation of full-field deformations at much smaller length scales than is possible using optical digital image correlation methods. However, the high spatial resolution of SEM-DIC comes at the cost of complex image distortions, long image scan times that can capture gradients from stress relaxation, and a high noise sensitivity to SEM parameters. In this paper, it is shown that these sources of error can significantly impact the quality of the results and must be accounted for in order to perform accurate SEM-DIC experiments. An existing framework for distortion corrections is adapted to improve accuracy and the procedures are described in detail. As the results demonstrate, time varying drift distortion is a larger problem at high magnification while spatial distortion is more problematic at low magnification. Additionally, the new use of sample-independent calibration and a method to eliminate the detrimental effects of stress relaxation in the displacement fields prior to distortion correction are introduced. The impact of SEM settings on image noise is quantified and noise minimization schemes are examined. Finally, a uniaxial tension test on coarse-grained 1100-O aluminum is used to demonstrate these techniques, where active slip planes are identified and strain localization is examined in relation to the underlying microstructure.

Digital Image Correlation under Scanning Electron Microscopy: Methodology and Validation

A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

Mechanisms for making and inspecting reticles

A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.

Semiconductor laser device and method of manufacturing the same

Design-based reticle inspection allows for a more efficient prioritization than typical human labor intensive reticle inspection techniques. A processed netlist for an integrated circuit (IC) and/or layout of the IC is used to determine the relative priorities of reticle defects identified by a reticle inspection device. In one embodiment, the processed netlist is a netlist that is derived by a verification tool based on a layout of the IC design. The processed netlist can include component coordinates that indicate the position of the components of the IC. In one embodiment, the processed layout includes derived geometry, for example, critical dimensions and/or device identifications that can be used to determine regions of interest. In one embodiment, defects are prioritized based on the location of the defects with respect to functional portions of the integrated circuit. For example, regions of interest can be determined around certain IC structures (e.g., transistor gates, minimum dimension lines, line corners). In one embodiment, defects within the regions of interest can be repaired while defects outside of the care zone can be ignored. More complex defect prioritization can be provided by prioritizing defects, for example, by size within the regions of interest. By prioritizing defects by areas of interest, the number of defects analyzed by a human operator and/or simulator can be decreased thereby decreasing the cost of reticle inspection and repair.

Design-based reticle defect prioritization

Techniques for determining wafer stage grid and yaw in a projection imaging tool are described. The techniques include exposing an overlay reticle onto a substrate having a recording media, thereby creating a plurality of printed fields on the substrate. The overlay reticle is then positioned such that when the reticle is exposed again completed alignment attributes are created in at least two sites in a first and a second printed field. The substrate is then rotated relative to the reticle by a desired amount. The overlay reticle is then positioned such that when the reticle is again exposed, completed alignment attributes are created in at least two sites in the first and a third printed field. Measurements of the complementary alignment attribute and a dynamic intra-field lens distortion are then used to reconstruct wafer stage grid and yaw error of the projection imaging system.

Method and apparatus for self-referenced dynamic step and scan intra-field scanning distortion

A rough pattern exceeding the resolution limit of light exposure is formed by light resolution. A fine pattern not exceeding the resolution limit of light exposure is formed by charge-beam exposure. Combining the rough pattern and the fine pattern produces a desired pattern. The sharing of the work between light exposure and charge-beam exposure exhibits the high throughput of light exposure and the excellent resolving power of charge-beam exposure.

Pattern-forming method and lithographic system

PROBLEM TO BE SOLVED: To provide a method with high accuracy for correcting proximity effect of electron beam exposure. SOLUTION: An underlying layer pattern 32 is classified. The pattern area density of a duplicated photolithographic layer pattern 33 with a photolithographic layer pattern 30 transferred to the upper layer of the underlying layer pattern 32 duplicated with the underlying layer pattern 32 and that of a pattern 31 without duplication are calculated each in a unit area, and then the correction for the proximity effect of the electron beam exposure is performed. COPYRIGHT: (C)2004,JPO

Method for correcting proximity effect of electron beam exposure, exposure method, method for manufacturing semiconductor device, and module for correcting proximity

A method for correcting a proximity effect applied to a dose of an electron beam exposure, includes classifying an underlying pattern of a level underlying a thin film layer; dividing a processing pattern to be transferred on the thin film layer into a first pattern overlapping with the underlying pattern and a second pattern which does not overlap with the underlying pattern according to the classified underlying pattern; calculating a pattern area density for the first and second patterns in a unit region; and calculating a corrected dose for the processing pattern according to the pattern area density.

Method for correcting a proximity effect, an exposure method, a manufacturing method of a semiconductor device and a proximity correction module

Proximity effect correction method of electronic beam exposure and use thereof

PROBLEM TO BE SOLVED: To manufacture at a high yield a semiconductor laser having a substrate of several tens of microns in thickness. SOLUTION: A semiconductor laser wafer 5 is obtained by forming a crystal growth layer 32 and a surface electrode 34 on a semiconductor substrate 31 of several hundreds of microns in thickness, and a semiconductor laser chip 3 is obtained by cleaving the semiconductor laser wafer 5. A heat sink 4 is connected to the side of the crystal growth layer 32 of the semiconductor laser chip 3, and the backside of the substrate 31 is thinned off by several to several tens of microns, until it becomes 5 μm, for example, using a mechanical polishing nethod through etching or sputtering.

Shinji Sato

Papers

Pattern-forming method and lithographic system

Method for correcting proximity effect of electron beam exposure, exposure method, method for manufacturing semiconductor device, and module for correcting proximity

Method for correcting a proximity effect, an exposure method, a manufacturing method of a semiconductor device and a proximity correction module

Proximity effect correction method of electronic beam exposure and use thereof

Manufacture of semiconductor laser