A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.

Configurable electrical circuit having configurable logic elements and configurable interconnects

A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.

Registered logic macrocell with product term allocation and adjacent product term stealing

A dynamically reconfigurable array logic (DRAL) (l0) is capable of in-system logical reconfiguration in real time and comprises a RAM programmable logic array of bits (l2), each bit comprising a fuse connection between logic elements. I/O means (l4) are coupled to the RAM programmable logic array (l2) for logical selection of registered output. A first register (l6) is coupled for receiving data and high-level commands. A sequencer (l8) includes a pair of up/down counters and functions to generate addresses. A timing device (20) controls DMA transfers and issues READ and WRITE strobes. A second register (26) monitors outputs and functions as a comparator, in a first mode, and functions to load outputs during specified time intervals in a second mode.

Dynamically reconfigurable array logic

Disclosed is an integrated circuit having multiple programmable arrays providing customizable logic. The integrated circuit has at least a first programmable array receiving a plurality of first inputs and generating a plurality of first outputs as programmed by the user. Also, it includes a second programmable array receiving a plurality of second inputs and generating a plurality of second outputs as programmed by the user. A means for selectiving interconnecting the inputs and outputs from the first and second programmable arrays is provided so that the programmable signals generated can be selectively connected in series, in parallel, or in a combination of series and parallel. Also provided are buried state registers for storing signals as programmed by the user. The stored signals from the buried state registers are likewise selectively interconnected with the input signals and output signals to provide added flexibility and power for the logic designer utilizing the device of the present invention.

Multiple array customizable logic device

A cardiac mapping system simulator comprising a microprocessor for simulating the electrical signal propagation of a heartbeat as it moves across the surface of a heart. A series of impulses that mimic the electrophysiological waveform are generated forming a two-dimensional map depicting heart activity. The series of pulses are generated in accordance with predetermined patterns and applied to the inputs of a cardiac mapping system or electrophysiology (E.P.) lab equipment in order to assess the operating condition of the cardiac mapping system or E.P. lab equipment prior to use on patients.

Cardiac mapping system simulator

The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the circuit. The device includes a first logic array for producing product terms of the input signals, a second logic array for producing sum terms of the first logic array, a two-dimensionally arrayed flip-flop array and means for setting the state of the flip-flop array. The flip-flop array is arranged in a plurality of rows of stages each including a plurality of serially connected flip-flop circuits. The inputs of respective rows are connected to the outputs of the second logic array, the outputs of the setting means are applied to the inputs of respective stages and the outputs thereof are parallelly fed back to the first logic array.

Shinju Horiguchi

Papers

Programmable sequential logic circuit devices

Programmierbare sequentielle logische schaltungseinrichtung