In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool

/pdf/legup-high-level-synthesis-for-fpga-based-processor-5f2afx6pcn.pdf

LegUp: high-level synthesis for FPGA-based processor/accelerator systems

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.

/pdf/a-survey-and-evaluation-of-fpga-high-level-synthesis-tools-4pv9ke4ji3.pdf

A Survey and Evaluation of FPGA High-Level Synthesis Tools

It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of high-level synthesis topics.

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems

Nowadays, there is a trend to design complex, yet secure systems. In this context, the Trusted Execution Environment (TEE) was designed to enrich the previously defined trusted platforms. TEE is commonly known as an isolated processing environment in which applications can be securely executed irrespective of the rest of the system. However, TEE still lacks a precise definition as well as representative building blocks that systematize its design. Existing definitions of TEE are largely inconsistent and unspecific, which leads to confusion in the use of the term and its differentiation from related concepts, such as secure execution environment (SEE). In this paper, we propose a precise definition of TEE and analyze its core properties. Furthermore, we discuss important concepts related to TEE, such as trust and formal verification. We give a short survey on the existing academic and industrial ARM TrustZone-based TEE, and compare them using our proposed definition. Finally, we discuss some known attacks on deployed TEE as well as its wide use to guarantee security in diverse applications.

https://hal.archives-ouvertes.fr/hal-01246364/document

Trusted Execution Environment: What It is, and What It is Not

In general, standard benchmark suites are critically important for researchers to quantitatively evaluate their new ideas and algorithms. This paper proposes CHStone, a suite of benchmark programs for C-based high-level synthesis. CHStone consists of a dozen of large, easy-to-use programs written in C, which are selected from various application domains. This paper also analyzes the characteristics of the CHStone benchmark programs, which will be valuable for researchers to use CHStone for the evaluation of their new techniques. In addition, we present future challenges to be solved towards the practical high-level synthesis.

Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

In general, standard benchmark suites are critically important for researchers to quantitatively evaluate their new ideas and algorithms. This paper presents CHStone, a suite of benchmark programs for C-based high-level synthesis. CHStone consists of a dozen of large, easy-to-use programs written in C, which are selected from various application domains. This paper also presents synthesis results which will be served as a baseline for researchers to compare their new techniques with. In addition, we present a case study on function-level transformation using a program in the CHStone suite.

http://www.yxi.com/applications/iscas2008-300_1027.pdf

CHStone: A benchmark program suite for practical C-based high-level synthesis

This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

RTOS-centric hardware/software cosimulator for embedded system design

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization.

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

Extending the idea of preemptive multitasking to DPRS (Dynamic Partial Reconfiguration Systems) has far-reaching implications as many mechanisms supporting the concept, such as context saving and restoring, have to be built practically from scratch. This paper addresses previously neglected issues, related to design of effective preemption mechanisms for Flip-Flop-based and RAM-based hardware tasks. Furthermore, a very efficient and complete solution to hardware task preemption for Virtex4-based DPRS is presented featuring in bitstream manipulation tool intended for PC and embedded system infrastructure with a DMA-based, instruction-driven reconfiguration/readback controller. Taking advantage of the developed lightweight bus, enhancing management of reconfigurable hardware modules, controller takes care of all essential hardware aspects related to context-switching thereby reducing CPU utilization to necessary minimum.

Shinya Honda

Papers

Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

CHStone: A benchmark program suite for practical C-based high-level synthesis

RTOS-centric hardware/software cosimulator for embedded system design

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems