Showing papers by "Shoji Otaka published in 2001"
Patent•
05 Nov 2001
TL;DR: In this article, a temperature compensation circuit comprises a signal source to output a first signal corresponding to a temperature change of an ambient temperature to a predetermined temperature, and a multiplier to multiply an external gain control signal and the first signal and output a second signal proportional to the temperature change.
Abstract: A temperature compensation circuit comprises a signal source to output a first signal corresponding to a temperature change of an ambient temperature to a predetermined temperature, and a multiplier to multiply an external gain control signal and the first signal and output a second signal proportional to the temperature change and the first signal to a variable gain amplifier to perform the temperature compensation with respect to the variable gain amplifier.
12 citations
Journal Article•
10 citations
Proceedings Article•
01 Jan 2001TL;DR: In this article, a 7 GHz low noise amplifier (LNA) was designed and fabricated using 0.25µm-CMOS technology and a cascode configuration with a dual-gate MOSFET and shielded pads was adopted to improve the gain and the noise performances.
Abstract: A 7-GHz low noise amplifier (LNA) was designed and fabricated using 0.25µm-CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads are adopted to improve the gain and the noise performances. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. The associated gain of 8.9dB, minimum noise figure of 1.8dB and input-referred 3rd-order intercept point of +8.4dBm were obtained at 7GHz. The LNA consumes 6.9mA from a 2.0V supply voltage. These measured results indicate the feasibility of a CMOS LNA with the appropriate techniques for low-noise and high-linearity applications over 5GHz.
4 citations
Patent•
05 Jul 2001TL;DR: An image suppression filter circuit comprises a first phase shifter outputting a first output signal and a second output signal substantially orthogonal to the first signal, a first adder adding the second and third output signals, a third phase shifters outputting an output signal orthogonally to the fifth and the sixth output signals as mentioned in this paper.
Abstract: An image suppression filter circuit comprises a first phase shifter outputting a first output signal and a second output signal substantially orthogonal thereto, a second phase shifter outputting a third output signal and a fourth output signal orthogonal to the third output signal, a first subtracter subtracting the fourth output signal from the first output signal, a first adder adding the second and third output signals, a third phase shifter outputting a fifth output signal and a sixth output signal orthogonal to the fifth output signal, a fourth phase shifter outputting a seventh output signal and an eighth output signal orthogonal thereto, a second subtracter subtracting the eighth output signal from the fifth output signal, and a second adder adding the sixth and the seventh output signals.
3 citations