Wireless systems where the nodes operate on batteries so that energy consumption must be minimized while satisfying given throughput and delay requirements are considered. In this context, the best modulation strategy to minimize the total energy consumption required to send a given number of bits is analyzed. The total energy consumption includes both the transmission energy and the circuit energy consumption. For uncoded systems, by optimizing the transmission time and the modulation parameters, it is shown that up to 80% energy savings is achievable over nonoptimized systems. For coded systems, it is shown that the benefit of coding varies with the transmission distance and the underlying modulation schemes.

Energy-constrained modulation optimization

An antenna apparatus, which can increase capacity in a cellular communication system or Wireless Local Area Network (WLAN), such as an 802.11 network, operates in conjunction with a mobile subscriber unit or client station. At least one antenna element is active and located within multiple passive antenna elements. The passive antenna elements are coupled to selectable impedance components for phase control of re-radiated RF signals. Various techniques for determining the phase of each antenna element are supported to enable the antenna apparatus to direct an antenna beam pattern toward a base station or access point with maximum gain, and, consequently, maximum signal-to-noise ratio. By directionally receiving and transmitting signals, multipath fading is greatly reduced as well as intercell interference.

Adaptive antenna for use in wireless communication systems

Multi-touch touch-sensing devices and methods are described herein. The touch sensing devices can include multiple sense points, each located at a crossing of a drive line and a sense line. In some embodiments, multiple drive lines may be simultaneously or nearly simultaneously stimulated with drive signals having unique characteristics, such as phase or frequency. A sense signal can occur on each sense line that can be related to the drive signals by an amount of touch present at sense points corresponding to the stimulated drive lines and the sense line. By using processing techniques based on the unique drive signals, an amount of touch corresponding to each sense point can be extracted from the sense signal. The touch sensing methods and devices can be incorporated into interfaces for a variety of electronic devices such as a desktop, tablet, notebook, and handheld computers, personal digital assistants, media players, and mobile telephones.

Simultaneous sensing arrangement

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10deg for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

A 24-GHz SiGe phased-array receiver-LO phase-shifting approach

An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

Integrated circuit device and electronic instrument

A CMOS variable-gain amplifier (VGA) using subthreshold exponential region transistors with master-slave control technique is proposed. The proposed technique is applied to an intermediate-frequency VGA with a quadrature demodulator for wireless receivers. The test chip is fabricated using a 0.25-/spl mu/m CMOS technology. An 80-dB linearly controlled gain range is achieved with exponential voltage-to-current converters using MOS transistors biased in a subthreshold exponential region, and the master-slave control circuits make the gain-control characteristic insensitive to the temperature. The experimental results indicate that the proposed technique is effective for a CMOS variable-gain amplifier.

A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range

To reduce DC offset caused by local-oscillator-signal self-mixing in a direct-conversion receiver, an active balanced harmonic mixer with second-order intermodulation (IM2) canceler was proposed, and a direct downconverter containing the mixer and a 45/spl deg/ phase shifter was fabricated on a BiCMOS chip. The dc offset caused by the self-mixing was measured and found to be smaller than the noise level. A second-order intercept point at the input of +37 dBm was achieved with the IM2 canceler, which is suitable for direct conversion receivers for quadrature phase-shift keying signals containing an amplitude modulation component.

An I/Q active balanced harmonic mixer with IM2 cancelers and a 45/spl deg/ phase shifter

A new digital background calibration technique for gain mismatches and sample-time mismatches in a Time-Interleaved Analog-to-Digital Converter (TI-ADC) is presented to reduce the circuit area. In the proposed technique, the gain mismatches and the sample-time mismatches are calibrated by using pseudo aliasing signals instead of using a bank of adaptive FIR filters which is conventionally utilized. The pseudo aliasing signals are generated and subtracted from an ADC output. A pseudo aliasing generator consists of the Hadamard transform and a fixed FIR filter. In case of a two-channel 10-bit TI-ADC, the proposed technique reduces the requirement for a word length of the FIR filter by about 50% without a look-up table (LUT) compared with the conventional technique. In addition, the proposed technique requires only one FIR filter compared with the bank of adaptive filters which requires (M-1) FIR filters in an M-channel TI-ADC.

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal

A frequency converter includes a high-frequency signal input circuit for forming a high-frequency signal with bias voltage or current to output a bias-added high-frequency signal; a local oscillation signal input circuit having a first element for forming a local oscillation signal with bias voltage or current and an element for suppressing a noise component having a frequency near a frequency of multiple of even number of a local oscillation frequency to output a bias-added and noise suppressed local oscillation signal; and a multiplication circuit for multiplying the bias-added high-frequency signal and the bias-added and noise suppressed local oscillation signal. By the constitution, it is possible to convert the high-frequency signal into a desired frequency signal having low influence of noises having frequency near the frequency of multiple of even number especially zero or two of the local oscillation signal to thereby reasonably suppress gain and noise in the high-frequency amplifier and local oscillator and reducing a current consumption of a radio receiver.

Frequency converter capable of reducing noise components in local oscillation signals

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm times 1.4 mm

Takafumi Yamaji

Papers

A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range

An I/Q active balanced harmonic mixer with IM2 cancelers and a 45/spl deg/ phase shifter

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal

Frequency converter capable of reducing noise components in local oscillation signals

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers