S
Shuichi Kameyama
Researcher at Panasonic
Publications - 20
Citations - 401
Shuichi Kameyama is an academic researcher from Panasonic. The author has contributed to research in topics: Semiconductor device & Field-effect transistor. The author has an hindex of 13, co-authored 20 publications receiving 401 citations.
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Patent
Method of fabricating a polycidegate employing nitrogen/oxygen implantation
TL;DR: In this article, a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, another step of formulating an ion implanted layer by implanting nitrogen ions into the poly-silicon conductor film, and the last step of creating a low resistance conductor of titanium on the non-monocyrstalline conductor film is described.
Patent
Method for making semiconductor transistor device by implanting punch through stoppers
TL;DR: In this article, a gate electrode is removed for self-alignment to selectively implant impurities only into end portions of a source region and a drain region, and the impurity concentration in the channel region is ununiform.
Patent
Method for producing a field-effect type semiconductor device
TL;DR: In this paper, a method for producing field-effect type semiconductor devices is disclosed, which includes the steps of: forming a gate insulator film on a semiconductor substrate; forming a conductor film on the gate-insulator film; and implanting impurity ions in the semiconductor substrategies through the gate and the conductor film for the purpose of controlling a threshold voltage of the device.
Patent
Field effect semiconductor device and its manufacturing method
Shuichi Kameyama,Atsushi Hori +1 more
TL;DR: In this article, a gate-drain overlap structure of excellent performance and reliability is presented for a semiconductor integrated circuit device using a field effect transistor, such as MOS, having the end part of the drain overlapped with the gate electrode.
Patent
Method for fabricating a semiconductor device by high energy ion implantation while minimizing damage within the semiconductor substrate
TL;DR: In this article, a damaged layer and a dopant layer are formed within the silicon substrate, through a plurality of repeated high energy ion implantation and subsequent annealing, in order to obtain the desired dopant concentration, density of secondary defect occurrences may be lowered.