Concurrent logic languages are high-level programming languages for parallel and distributed systems that offer a wide range of both known and novel concurrent programming techniques. Being logic programming languages, they preserve many advantages of the abstract logic programming model, including the logical reading of programs and computations, the convenience of representing data structures with logical terms and manipulating them using unification, and the amenability to metaprogramming. Operationally, their model of computation consists of a dynamic set of concurrent processes, communicating by instantiating shared logical variables, synchronizing by waiting for variables to be instantiated, and making nondeterministic choices, possibly based on the availability of values of variables.This paper surveys the family of concurrent logic programming languages within a uniform operational framework. It demonstrates the expressive power of even the simplest language in the family and investigates how varying the basic synchronization and control constructs affect the expressiveness and efficiency of the resulting languages.In addition, the paper reports on techniques for sequential and parallel implementation of languages in this family, mentions their applications to date, and relates these languages to the abstract logic programming model, to the programming language PROLOG, and to other concurrent computational models and programming languages.

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The family of concurrent logic programming languages

This article surveys the major developments in sequential Prolog implementation during the period 1983–1993. In this decade, implementation technology has matured to such a degree that Prolog has left the university and become useful in industry. The survey is divided into four parts. The first part gives an overview of the important technical developments starting with the Warren abstract machine. The second part presents the history and the contributions of the major software and hardware systems. The third part charts the evolution of Prolog performance since Warren's DEC-10 compiler. The fourth part extrapolates current trends regarding the evolution of sequential logic languages, their implementation, and their role in the marketplace.

1983–1993: The wonder years of sequential Prolog implementation

Model elimination and connection tableau procedures

This report surveys the major developments in sequential Prolog implementation during the period 1983–1993. In this decade, implementation technology has matured to such a degree that Prolog has left the university and become useful in industry. The survey is divided into four parts. The first part gives an overview of the important technical developments starting with the Warren Abstract Machine (WAM). The second part presents the history and the contributions of the major software and hardware systems. The third part charts the evolution of Prolog performance since Warren’s DEC-10 compiler. The fourth part extrapolates current trends regarding the evolution of sequential logic languages, their implementation, and their role in the marketplace.

http://www.hpl.hp.com/techreports/Compaq-DEC/PRL-RR-36.pdf

The Wonder Years of Sequential Prolog Implementation

Most Prolog machines have been based on specialized architectures. Our goal is to start with a general purpose architecture and determine a minimal set of extensions for high performance Prolog execution. We have developed both the architecture and optimizing compiler simultaneously, drawing on results of previous implementations. We find that most Prolog specific operations can be done satisfactorily in software; however, there is a crucial set of features that the architecture must support to achieve the best Prolog performance. The emphasis of this paper is on our architecture and instruction set. The costs and benefits of the special architectural features and instructions are analyzed. Simulated performance results are presented and indicate a peak compiled Prolog performance of 3.68 million logical inferences per second.

Fast Prolog with an extended general purpose architecture

Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).

A Personal Sequential Inference Machine, called PSI, is a personal computer designed as a software development tool for the Fifth Generation Computer Systems (FGCS) project. PSI has a logic based, highlevel machine instruction set, called Kernel Language Version 0 (KL0). The machine architecture of PSI is specialized for direct execution of KL0. “Unification” and “backtracking” are the principal operations in Logic Programming, and they are efficiently performed by PSI hardware/ firmware. Its estimated execution speed is 20K to 30K LIPS. The machine is also equipped with a large main memory with a maximum of 40 bits×16M words. This paper presents the key points of its design and the features of its machine architecture.

The design and implementation of a personal sequential inference machine: PSI

PSI is a personal computer system being developed as a tool for providing researchers with an efficient programming environment It directly supports logic programming language, KL0 (Fifth Generation Kernel Language, Version 0), with firmware and hardware Its interpreter is implemented in the firmware and several hardware mechanisms are provided to attain almost the same level of performance as the DEC-10 Prolog on DEC2060 It also provides the user with a large memory space, 40 bits × 2 to 16 MW, which is essential for developing actual application programs like an expert system To make efficient man-machine interaction possible, such input and output devices as bit-map display, pointing device and key-board are provided A local area network is also being developed to build a distributed system

Shunichi Uchida

Papers

Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).

The design and implementation of a personal sequential inference machine: PSI

Outline of the Personal Sequential Inference machine: PSI

A Microprogrammed Interpreter for the Personal Sequential Inference Machine.

Research and Development of the Parallel Inference System in the Intermediate Stage of the FGCS Project.