There have been several strategies proposed to realise adiabatic circuits. Most of them require a clock signal and also its complement form. In this investigation, the authors we propose a family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Measurements of energy drawn, recovered and dissipated have been carried out through simulation and, they are the same as obtained from the theoretical expression. In the proposed circuit, the input and output logic levels are approximately the same and can be used for building cascaded logic circuits. The energy saving in this family is to the tune of 50% compared with CMOS circuits constructed with similar circuit parameters, up to 250 MHZ. The authors have described the proposed inverter, NAND gates, NOR gates, adder circuits and JK flip-flop along with their simulation results.

Cascadable adiabatic logic circuits for low-power applications

Energy storage technology is becoming more and more important in today's environmentally conscious society. In the conventional method of directly charging a capacitor under a constant power supply voltage, the amount of energy dissipation is the same as the energy stored in the capacitor. In this paper, we propose the stepwise charging of a capacitor by consecutively changing the duty ratio of the DC-DC down converter. In $ {\rm N} $ step charging, the energy dissipation is reduced to one Nth when compared with the conventional direct charging. The reduction of the dissipated energy is verified by SPICE simulations and by breadboard experiments, through which an energy reduction of one fourth and one eighth is confirmed from the measured power supply currents in four and eight step charging, respectively.

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio

This paper presents a new adiabatic logic which drives two-phase clocking. The proposed adiabatic logic (2PC2AL) uses two trapezoidal-wave pulses and resembles behavior of static CMOS. The structure of 2PC2AL can be directly derived from static CMOS logic circuits. We also propose a trapezoidal-wave generator compatible to 2PC2AL. The proposed clock generator is based on the switched capacitor circuit. From the simulation results, we show that the energy consumption of the proposed circuit is lower than that of CMOS logic circuits in the range of from 1 to 100 MHz, and the 4-bit multipliers also are about 30n50% lower.

/pdf/two-phase-clocked-cmos-adiabatic-logic-4a5n3uzb96.pdf

Two-phase Clocked CMOS Adiabatic Logic

The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory.

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

A single-bit-line (BL) static RAM (SRAM) circuit that employs adiabatic charging of a word line during a read operation was found to provide a large dynamic noise margin (DNM) for reading. Single-BL reading is achieved by using a left access transistor and a shared reading port. The shared reading port greatly reduces the BL capacitance, enabling the voltage of the BL connected to the low-voltage node of the flip-flop to change from the precharge voltage to GND. An analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit. This circuit enables the design of an SRAM that is smaller than a conventional one, resulting in lower energy consumption.

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

Shunji Nakata

Papers

Adiabatic Charging Reversible Logic Using a Switched Capacitor Regenerator