This work presents a configurable architecture for an artificial neural network implemented with a Field Programmable Gate Array (FPGA) in a System on Chip (SoC) environment. This architecture can reproduce the transfer function of different Multilayer Feedforward Neural Network (MFNN) configurations. The functionality of this configurable architecture relies on a single perceptron, multiplexers, and memory blocks that allow routing, storing, and processing information. The extended Kalman filter is the training algorithm that obtains the optimal weight values for the MFNN. The presented architecture was developed using Verilog Hardware Description Language, which permits designing hardware with a fair number of logical resources, and facilitates the portability to different FPGAs models without compatibility problems. A SoC that mainly incorporates a microprocessor and a FPGA is proposed, where the microprocessor is used for configuring the the MFNN and to enable and disable some functional blocks in the FPGA. The hardware was tested with measurements from a GaN class F power amplifier, using a 2.1 GHz Long Term Evolution signal with 5 MHz of bandwidth. In particular, a special case of an MFNN with two layers, i.e., a real-valued nonlinear autoregressive with an exogenous input neural network, was considered. The results reveal that a normalized mean square error value of −32.82 dB in steady-state was achievable, with a 71.36% generalization using unknown samples.

https://www.mdpi.com/2079-9292/8/7/761/pdf

SoC Design Based on a FPGA for a Configurable Neural Network Trained by Means of an EKF

In this paper, a universal asynchronous receiver and transmitter (UART) are described, which is basically a serial data transmission protocol used in digital circuit applications. The architecture of the UART transmitter has a baud rate generator, parity generator, transmitter finite state machine (FSM) and parallel in serial out register (PISO). UART receiver has a baud rate generator, negative edge detector, parity checker, receiver finite state machine (FSM) and serial in parallel out (SIPO) register. The baud rate generator of both transmitter and receiver is the same, so the baud rate of transmitter/receiver is the same. Baud rate generator is the same as the frequency divider circuit. The data frame of the UART transmitter is 1 start bit, 8 transmits data bits, 1 parity bit and 1 stop bit. The baud rate of the transmitter and receiver is 4 Mbps using the system clock of 64 MHz’s. Implementation, simulation, and synthesis is done Xilinx Vivado 2016.2 version tool. The design is verified using simulated waveform and synthesized on the FPGA Zed board.

Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)

Improvements for the applicability of power-watermarking to embedded IP cores protection

The UART(Universal Asynchronous Receiver and transmitter) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. SPI is a common technology used nowadays for communication with peripheral devices where we want to transfer data speedily and with in real time constraints. In the existing work data acquisition system for underground has been designed for counters triggered by surface detectors and they have used UART and SPI protocol for the communication with dedicated processor. In this paper we have used Xilinx 12.4i and SPARTAN 3E FPGA to implement the whole system. The hyper terminal is used to check the UART protocol and 12 bit DAC MCP4922 used for check SPI protocol. The proposed work can provides both protocol effectively for the wireless serial communication. These serial protocols mainly used in Zigbee wireless technology.

Design implementation of UART and SPI in single FGPA

This paper presents a novel Field Programmable Gate Array (FPGA) architecture for hardware implementation of Multilayer Feedforward Neural Networks (MFNNs) suitable for Digital Pre-Distortion (DPD) technique. This architecture consists of a single neuron, several storage units and multiplexors that allow the reconfiguration via software of the FPGA to handle different numbers of inputs, layers, neurons and threshold functions of the MFNN. This novel FPGA architecture offers the advantage of using FPGAs with less logical resources than those found in a Virtex-6. The usefulness of this novel FPGA architecture is demonstrated by the modeling of the AM-AM and AM-PM characteristics of a GaN class F PA and a Doherty PA in a Virtex-6 FPGA from Xilinx configured with two different MFNNs, using a 2.1 GHz LTE signal of 5 MHz of bandwidth. The results obtained with the FPGA implementation are compared with data computed with MATLAB achieving Normalize Mean Square Error (NMSE) better than −50 dB.

A novel configurable FPGA architecture for hardware implementation of multilayer feedforward neural networks suitable for digital pre-distortion technique

The proposed paper describes the universal asynchronous receiver/transmitter i.e. UART which is the kind of serial communication protocol which allows the full duplex communication in serial link. This paper presents the hardware implementation of a high speed and efficient UART using FPGA. The UART consists of three main components namely transmitter, receiver and baud rate generator which is nothing but the frequency divider. This has been simulated on ModelSim SE 10.0a and has been implemented by using Verilog description language which has been synthesized on FPGA kits such as Virtex4 and Spartan3.

Shweta Gaba

Papers

Synthesis and Implementation of UART Using VHDL Codes