An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Plastic integrated circuit package and method and leadframe for making the package

An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.

Ultra high density integrated circuit packages method

Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Semiconductor chip assemblies, methods of making same and components for same

An apparatus and method for increasing integrated circuit density comprising utilizing chips with both direct (flip chip type) chip to conductors connection technology and wire bonds and/or TAB. An aspect of the present invention comprises at least one semiconductor die with a face surface having both flip chip type electric connections and bond pads for wirebonding or TAB attachment thereof to at least one leadframe. Another aspect of the present invention comprises using two pair of back to back attached dice with leadframe lead fingers disposed between the dice pairs. The die face surfaces adjacent to the lead fingers are in direct electrical communication therewith via flip-chip type connectors. Bond pads on the die face surface facing outward from the lead fingers are electrically connected to the leadframe via wire bonds and/or TAB.

Combination of semiconductor interconnect

The present invention is directed to a packaged semiconductor chip which effectively dissipates heat and has improved performance. The packaged chip has a plurality of lead frame conductors extending through the encapsulating material which are adhesively joined to the semiconductor chip, preferably by means of an alpha barrier. The conductors cover a substantial portion of the surface of the chip and thereby serve as conduits for the dissipation of heat from the chip. Wires are bonded to the conductors and extend from the conductors to the terminals on the semiconductor chip. In a preferred embodiment the semiconductor chip terminals are located along a center line of the chip. This allows for short connecting wires which in turn contribute to faster chip response.

Package semiconductor chip

A method of forming semiconductor devices wherein a continuous metallic sheet is cut under computer control into a personalized lead pattern. The pattern is then moved to a bonding station. A bonding tool actuated by computer control moves from one terminal end to another to sequentially bond terminals to the semiconductor device. A variety of various patterns and chips can be handled on the same line using common cutting and bonding tools. A second bond can be made from the lead pattern to either a lead frame or a substrate.

Highly integrated universal tape bonding

@ A packaged semiconductor chip which effectively dissipates heat and has improved performance. The packaged chip has a plurality of lead frame conductors (38) extending through the encapsulating material (46) which are adhesively joined to the semiconductor chip (34), preferably by means of an alpha barrier (32). The conductors (38) cover a substantial portion of the surface of the chip (34) and thereby serve as conduits for the dissipation of heat from the chip. Wires (58) are bonded to the conductors and extend from the conductors to the terminals (52) on the semiconductor chip. In a preferred embodiment the semiconductor chip terminals (52) are located along a center line of the chip. This allows for short connecting wires (58) which in turn contribute to faster chip response.

Packaged semiconductor chip

A method of forming semiconductor devices wherein a continuous metallic sheet (14) is cut (16, 18) under computer (10) control into a personalized lead pattern. The pattern is then moved to a bonding station (40). A bonding tool (32) actuated by computer control moves from one terminal end to another to sequentially bond terminals to the semiconductor device (26). A variety of various patterns and chips can be handled on the same line using common cutting and bonding tools. A second bond can be made from the lead pattern to either a lead frame (30) or a substrate (50).

Highly integrated universal tape bonding of semiconductor chips

A method and apparatus for improved percussive arc welding is disclosed. In this technique a test arc of a voltage no greater than the initiating voltage of the percussive arc welding is first applied across the pieces to be welded. The welding cycle is then performed if, and only if, an arc is detected responsive to the impressing of the test voltage.

Sigvart J. Samuelsen

Papers

Package semiconductor chip

Highly integrated universal tape bonding

Packaged semiconductor chip

Highly integrated universal tape bonding of semiconductor chips

Percussive arc welding