Showing papers by "Simon Deleonibus published in 1992"

Isolation design comparisons for 0.5 μm CMOS technology using SILO process

Abstract: SILO process with R.T.N. of silicon is an alternative isolation scheme, which provides both small field encroachment and rigorous isolation with 0.8 μm active area spacing. Two field doping processes were developed for 0.5 μm CMOS technology and were extensively compared.