Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

This chapter introduces an overview of the main reliability threats of last nanoscale generations of CMOS technology designs. In particular, the chapter focuses on sources of process variability and their impact on circuit design and their performances, but also on the runtime variability such as voltage fluctuations as well soft errors. Further to that we go over the transistor aging provoked by different wear-out physical effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Random Telegraph Noise (RTN) and Time-Dependent Dielectric Breakdown (TDDB). 1 Reliability Issues With aggressive downscaling of CMOS technology into deep nanometer, reliability has become a major issue [1]. In this section, the general sources of reliability issues in current technology nodes are briefly explained. The sources of unreliability in current technology nodes can be categorized into three different categories: (i) variability issues, (ii) transient faults and soft errors (iii) permanent faults, all of them closely related to the fabrication process and to actual economical and physical difficulties to further improve the fabrication process [2], to the stochastic fluctuations of dopants in transistor channel and the thin oxide thickness [3] and to the intrinsic mechanisms of transistor and interconnect aging [4]. S. Kiamehr M.B. Tahoori (&) Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany e-mail: mehdi.tahoori@kit.edu S. Kiamehr e-mail: kiamehr@kit.edu L. Anghel Grenoble Institute of Technology, Phelma, Grenoble Cedex, France e-mail: lorena.anghel@imag.fr © Springer International Publishing AG 2018 M. Ottavi et al. (eds.), Dependable Multicore Architectures at Nanoscale, DOI 10.1007/978-3-319-54422-9_1 3 Due to variability, the devices/gates/circuits characteristics are different from the intended designed ones. The variability could be due to “time-zero” variation (process variation) or runtime variation such as voltage and temperature variations. Process variation is a natural device parameter variation which makes the properties of fabricated devices different from that of designed ones. In other words, due to process variation different similarly designed transistors/gates will perform (operate) with parametric differences after fabrication. Due to runtime variation, the transistors/gates properties will change (degrade) during the chip operational lifetime. Runtime variations are routed in different sources such as voltage variation and temperature variation. The voltage and temperature variations are temporal or spatial according to the place of the transistor/gate and they depend on the workload, frequency and time of operation. Therefore, they cause variation on the properties of different transistors/gates at different locations of the circuit and at different time points during the chip operational lifetime. Transistor aging is a source of runtime variations caused by different wear-out effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) and soft Time-Dependent Dielectric Breakdown (soft TDDB), which in turn are dependent on process and runtime variations. All these effects cause the threshold voltage of the transistors to increase and hence the switching delay of the gates that containing these transistors increases which can eventually lead to parametric timing failures if the delay of the circuit does not meet the timing constraints. In order to deal with these sources of variation, traditional approaches consist in improving the technology process as much as possible, or to add guard-banding as a common approach at the design level. In the guard-banding approach, a timing margin is added to the designed clock cycle to guarantee the correct operation of the circuit during the operational lifetime. A pessimistic guard-banding leads to a performance loss and optimistic guard-banding results in a low reliability of the chip. Therefore, the required timing margin needs to be accurately predicted. Figure 1 shows the components of the required timing margin for IBM Power7+ processor [5]. As shown in this figure, the main components of the timing margin are uncertainty (e.g. global and local process variation), wearout (transistor aging) and voltage and thermal variations. Fig. 1 Components of chip guard-band for the IBM Power7+ [5] 4 S. Kiamehr et al.

Dependable Multicore Architectures at Nanoscale

The down-scaling of CMOS technologies into the nano-regime and the advent of the Internet of Things (IoT) era jointly conspire to elevate wearout effects to the status of major reliability threats. Bias temperature instability (BTI) and Electromigration (EM) are two of the dominant wearout mechanisms which affect transistors and on-chip interconnect, respectively. Both phenomena have been shown to exhibit partial recovery, but this property has been treated only as a side effect until now since passive recovery is slow and ineffective due to the permanent portion of wearout. In this paper, we propose and demonstrate that recovery for both wearout mechanisms can be further activated and accelerated, such that the permanent portion of wearout can be fully eliminated by using in-time scheduled recovery. We show that the explored recovery properties can be utilized effectively for reducing the wearout-induced design margins, this approach introducing a new design dimension by reducing the effects of wearout in a fundamental way. A novel circuit scheme and potential implementations at the system level that can assist both BTI and EM recovery are also detailed in the paper.

Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery

This thesis proposes optimisation methods for improving the performance of circuits implemented on a custom reconfigurable hardware platform with knowledge of intrinsic variations, through the use of digital reconfiguration. With the continuing trend of transistor shrinking, stochastic variations become first order effects, posing a significant challenge for device reliability. Traditional device models tend to be too conservative, as the margins are greatly increased to account for these variations. Variation-aware optimisation methods are then required to reduce the performance spread caused by these substrate variations. The Programmable Analogue and Digital Array (PAnDA) is a reconfigurable hardware platform which combines the traditional architecture of a Field Programmable Gate Array (FPGA) with the concept of configurable transistor widths, and is used in this thesis as a platform on which variability-aware circuits can be implemented. A model of the PAnDA architecture is designed to allow for rapid prototyping of devices, making the study of the effects of intrinsic variability on circuit performance – which requires expensive statistical simulations – feasible. This is achieved by means of importing statistically-enhanced transistor performance data from RandomSPICE simulations into a model of the PAnDA architecture implemented in hardware. Digital reconfiguration is then used to explore the hardware resources available for performance optimisation. A bio-inspired optimisation algorithm is used to explore the large solution space more efficiently. Results from test circuits suggest that variation-aware optimisation can provide a significant reduction in the spread of the distribution of performance across various instances of circuits, as well as an increase in performance for each. Even if transistor geometry flexibility is not available, as is the case of traditional architectures, it is still possible to make use of the substrate variations to reduce spread and increase performance by means of function relocation.

Variability-aware circuit performance optimisation through digital reconfiguration

Analog and mixed-signal (AMS) blocks are often a crucial and time-consuming part of System-on-Chip (SoC) design, primarily due to a manual circuit and layout iterations. Existing automated solutions for selecting circuit parameters for a given target specification are often not efficient, accurate, or reliable. In order for an automated sizing tool to be practical, we posit that it must: 1) return valid results for a large range of target specifications; 2) understand where and why it is unable to meet certain specifications; 3) consider true layout parasitic simulations for complete end-to-end design; and 4) be automated, allowing most of the design effort to fall on the tool. In this article, we address these critical points by establishing an automated reinforcement learning framework, AutoCkt, by 1) successfully deploying it on a complex two-stage transimpedance amplifier and two-stage folded cascode with biasing in the 16-nm FinFet technology; 2) implementing a new combined distribution deployment algorithm to improve efficiency; 3) analyzing in-depth the efficacy of the trained agent; and 4) demonstrating the functionality of this tool when considering a topology that is highly sensitive to layout parasitics. Our algorithm not only successfully reaches unique, valid, and practical performances, but also does so in state-of-the-art run time, up to 38X more efficient than prior work. In addition, our tool averages just four parasitic simulations obtained by using the Berkeley Analog Generator, to achieve a target specification post-layout for the folded cascode. AutoCkt successfully generates LVS-passed designs with validation in process corner variation results. 

Automated Design of Analog Circuits Using Reinforcement Learning

The nanometre technology is different fundamentally from its predecessors as it is exposed to a wide variety of new effects that are induced on the transistor chips. NBTI is one degradation effects in the reliability regime. It plays significant role as it leads to severe performance degradation. Ageing in pMOS transistor takes place due to Negative bias temperature instability (NBTI) which is the major threat to reliability as we scale down the transistor geometries consistently towards our objective for less power consumption coupled with high performance. The work presented in this paper focuses on NBTI detection scheme for building tolerance with respect to NBTI effects employing Adaptive Body Bias (ABB). In this scheme, an On-Chip monitor detects the change in threshold voltage of the circuit to generate corresponding adaptive body bias by the body biasing circuit which is supplied to the transistors. The simulations have been carried out taking V BB as zero, i.e., No Body Bias (NBB), by applying a finite adaptive body bias (ABB) voltage to the transistors on the chip & their corresponding power and delay have thus been calculated by implementation of the proposed approach on a host of domino logic circuits which include Current comparison domino (CCD). We have mitigated the rise in delay problem by suitably allocating a supply voltage so that the delay specifications are continuously met even after a time span of 10 years of operation at the cost of very low power headroom. Simulations have been performed using the BSIM4v4.7 model & 32-nm predictive technology model in SILVACO EDA tool at a frequency of 2 GHz and nominal supply voltage of 0.9V. The proposed approach has been implemented on 32-bit & 64-bit OR gates and also on 32-bit comparator and the results has been noteworthy.

NBTI detection methodology for building tolerance with respect to NBTI effects employing adaptive body bias

The nanometre scale technology is fundamentally different from its predecessors as they are exposed to a wide variety of new effects that are induced on the transistor chips. One of the reliability degradation effects is process variation which plays a relevant mantle as it leads to performance degradation. The work presented in this paper explains an all process corner (SS, SF, FS & FF) detection scheme for providing tolerance towards process variations using Adaptive Body Bias (ABB). In this scheme, an on-chip monitor detects the process corner at which the circuit is operating and a corresponding adaptive body bias is generated by the body biasing circuit which is supplied to the transistors. The simulations are performed taking V BB as 0, i.e., No Body Bias (NBB) and by supplying a finite adaptive body bias (ABB) voltage to the transistors on the chip and their corresponding mean and variance have been calculated using Monte Carlo histograms. Simulations have been performed on a critical path which has been extracted from a microprocessor at 32 nm predictive technology model using HSPICE. Monte Carlo simulations of 10,000 runs demonstrate that the proposed approach provides tolerance to process variations under all process corners. The proposed approach has shown to reduce the impact of process variations on frequency, dynamic power & leakage power and a reduction in the values of relative standard deviation (σ/μ) conforms to our circuit approach.

https://ieeexplore.ieee.org/iel7/7147630/7159156/07159326.pdf

A process corner detection methodology for resilience towards process variations using adaptive body bias

Transistor ageing has been a major problem as far as nanometre technology is concerned which leads to performance degradation and reliability issues. Ageing in pMOS transistor takes place due to Negative bias temperature instability (NBTI) which is a major threat in reliability as Iscale down the transistor geometries aggressively in our quest for low power and high performance. Overcoming ageing effect requires additional power expense, which in turn aggravates the power and heating problem. I propose an adaptive supply voltage (ASV) scheme as an arguably power efficient approach for variation resilience since it attempts to allocate power resources only where the negative effect of ageing is strong. Upon implementing the proposed approach on a host of domino logic circuits which include Current comparison domino (CCD) Ihave mitigated the rise in delay problem by suitably allocating a supply voltage so that the delay specifications are continuously met even after a lifespan of 10 years of operation at the expense of very low power headroom. Simulations have been performed using the BSIM4v4.7 model & 32 nm predictive technology model in SILVACO EDA tool at a frequency of 2 GHz and nominal supply voltage of 0.9V. The proposed approach has been implemented on 32 bit & 64 bit OR gates and also on 32 bit comparator and the results have been noteworthy.

Circuit level technique for mitigating effects of NBTI for wide fan-in domino logic circuits using supply voltage tuning

The effects of process variation exacerbates as we keep on aggressively scaling the device dimensions. Register files composed using domino logic structures are a crucial block in the critical path of the microprocessors and the adverse effects of process variations on these could lead to functional failure in a worst case scenario. Erroneous behaviour of circuits can give rise to high and varying power consumption and can prove to be expensive. To deal firmly with the adverse effects of process variations with the goal of reduced leakage current, feedback keeper architecture has been proposed in this paper. This keeper architecture adapts itself to the changing conditions and the circuit's performance metrics do not vary much even at the extreme process corners (SS to FF). Though the proposed keeper architecture incurs an area overhead of 16%, it provides high tolerance and reduces power consumption by nearly 42% at FF corner and by 32% at SS corner with respect to other existing designs. The reduction in the leakage current and evaluation contention are about 95% & 84% when compared to standard domino gate with footless scheme. All the simulations have been performed at 45nm & 32nm technologies on a host of domino logic circuits ranging from a 64:1 multiplexer to 32-bit comparator circuitry at using BSIM 4v4.7 model in SILVACO EDA tool at an operating frequency of 1.2 GHz.

Soumya Narang

Papers

NBTI detection methodology for building tolerance with respect to NBTI effects employing adaptive body bias

A process corner detection methodology for resilience towards process variations using adaptive body bias

Circuit level technique for mitigating effects of NBTI for wide fan-in domino logic circuits using supply voltage tuning

A modified variation-tolerant keeper architecture for evaluation contention & leakage current minimization for wide fan-in domino structures