This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

physical design electronics wikipedia in integrated circuit design physical design is a step in the standard design cycle which follows after the circuit design at this step circuit representations of, integrated circuit layout wikipedia integrated circuit layout also known ic layout ic mask layout or mask design is the representation of an integrated circuit in terms of planar geometric shapes, engineering courses concordia university concordia university http www concordia ca content concordia en academics graduate calendar current encs engineering courses html, peer reviewed journal ijera com international journal of engineering research and applications ijera is an open access online peer reviewed international journal that publishes research, telecommunications abbreviations and acronyms consultation erkan is pleased to provide this living document for unlocking the evergrowing vocabulary of abbreviations and acronyms of the telecommunications world, contents international information institute vol 7 no 3 may 2004 mathematical and natural sciences study on bilinear scheme and application to three dimensional convective equation itaru hataue and yosuke

Vlsi Physical Design From Graph Partitioning To Timing Closure

Spin–orbit torque (SOT) is an emerging technology that enables the efficient manipulation of spintronic devices. The initial processes of interest in SOTs involved electric fields, spin–orbit coupling, conduction electron spins, and magnetization. More recently, interest has grown to include a variety of other processes that include phonons, magnons, or heat. Over the past decade, many materials have been explored to achieve a larger SOT efficiency. Recently, holistic design to maximize the performance of SOT devices has extended material research from a nonmagnetic layer to a magnetic layer. The rapid development of SOT has spurred a variety of SOT-based applications. In this article, we first review the theories of SOTs by introducing the various mechanisms thought to generate or control SOTs, such as the spin Hall effect, the Rashba-Edelstein effect, the orbital Hall effect, thermal gradients, magnons, and strain effects. Then, we discuss the materials that enable these effects, including metals, metallic alloys, topological insulators, 2-D materials, and complex oxides. We also discuss the important roles in SOT devices of different types of magnetic layers, such as magnetic insulators, antiferromagnets, and ferrimagnets. Afterward, we discuss device applications utilizing SOTs. We discuss and compare three- and two-terminal SOT-magnetoresistive random access memories (MRAMs); we mention various schemes to eliminate the need for an external field. We provide technological application considerations for SOT-MRAM and give perspectives on SOT-based neuromorphic devices and circuits. In addition to SOT-MRAM, we present SOT-based spintronic terahertz generators, nano-oscillators, and domain-wall and skyrmion racetrack memories. This article aims to achieve a comprehensive review of SOT theory, materials, and applications, guiding future SOT development in both the academic and industrial sectors.

/pdf/roadmap-of-spin-orbit-torques-5gdnrw07hi.pdf

Roadmap of Spin–Orbit Torques

Security is a critical aspect in modern circuit design, but research into hardware security at the device level is rare as it requires modification of existing technology nodes. With the increasing challenges facing the semiconductor industry, interest in out-of-the-box security solutions has grown, even if this implies introducing novel materials such as two-dimensional layered semiconductors. Here, we show that high-performance, low-voltage, two-dimensional black phosphorus field-effect transistors (FETs) that have reconfigurable polarities are suitable for hardware security applications. The transistors can be dynamically switched between p-FET and n-FET operation through electrostatic gating and can achieve on–off ratios of 105 and subthreshold swings of 72 mV dec−1 at room temperature. Using the transistors, we create inverters that exhibit gains of 33.3 and are fully functional at a supply voltage of 0.2 V. We also create a security primitive circuit with polymorphic NAND/NOR obfuscation functionality with sub-1-V operation voltages, and the robustness of the polymorphic gate against power supply variations is tested using Monte Carlo simulations. Transistors that use two-dimensional black phosphorus as the active material can dynamically switch between p-type and n-type operation, and can be used to create security primitive circuits with polymorphic NAND/NOR obfuscation functionality.

Two-dimensional transistors with reconfigurable polarities for secure circuits

Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme—full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-of-line (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement- and routing-centric proximity attacks; correct connections are reduced by $7.47\times $ , and complexity is increased by $24.15\times $ , respectively, for such attacks.

Obfuscating the interconnects: low-cost and resilient full-chip layout camouflaging

This paper reports the first analog integrated spatio-spectral beamforming front-end. The proposed front-end allows for accurate beam steering of signals with large fractional bandwidths, thus minimizing beam squinting, and simultaneous and independent steering of multi-carrier signals. Different spatio-spectral beamforming strategies are discussed and compared. As a proof of concept, an 8 GHz 2-channel, 4-frequency phased-array beamformer is designed and implemented in 65 nm CMOS. The IF signal on each channel is frequency split using an all passive 4-point analog FFT. The orthogonal frequency outputs are then beam-steered using an all passive I-Q vector-combiner. The RF circuit draws 22.8 mA from a 1.2 V supply while the analog baseband consumes 135 μW at 120 MS/s (9 pJ/conv.).

Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays

Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

An analytical framework has been developed to describe the transient behavior of negative resistance injection-locked oscillators based on Adler's equation. Design insights are provided by using a combination of analytical simplifications and graphical interpretation. It has been shown that injection locking can be used to meet the requirements for fast hopping systems like the MBOA-UWB specification. The theoretical analysis and design solutions have been verified by extensive simulations on real CMOS processes.

Understanding the Transient Behavior of Injection Locked LC Oscillators

Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network flow-based proximity attack, proposed by Wang et al. (DAC'16) [1], has demonstrated that most prior art on split manufacturing is highly vulnerable. Here in this work, we present two practical layout techniques towards secure split manufacturing: (i) gate-level graph coloring and (ii) clustering of same-type gates. Our approach shows promising results against the advanced proximity attack, lowering its success rate by 5.27x, 3.19x, and 1.73x on average compared to the unprotected layouts when splitting at metal layers M1, M2, and M3, respectively. Also, it largely outperforms previous defense efforts; we observe on average 8x higher resilience when compared to representative prior art. At the same time, extensive simulations on ISCAS'85 and MCNC benchmarks reveal that our techniques incur an acceptable layout overhead. Apart from this empirical study, we provide — for the first time — a theoretical framework for quantifying the layout-level resilience against any proximity-induced information leakage. Towards this end, we leverage the notion of mutual information and provide extensive results to validate our model.

Satwik Patnaik

Papers

Obfuscating the interconnects: low-cost and resilient full-chip layout camouflaging

Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Understanding the Transient Behavior of Injection Locked LC Oscillators

Rethinking split manufacturing: an information-theoretic approach with secure layout techniques