A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Delay line calibration

Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.

Multi-phase clock generation

Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.

RC oscillator based on delay-free comparator

A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.

DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus

In described examples, a relaxation oscillator (100) reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current (II) and a second current (12), so that after the first current (II) has been input to a first pair of circuits (120, 140) and the second current (12) has been input to a second pair of circuits (130, 140), the second current (12) is input to the first pair of circuits (120, 140), and the first current (II) is input to the second pair of circuits (130, 140).

Relaxation oscillator with current and voltage offset cancellation

A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation

A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed The DLL includes a delay line, and a control module The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal The delay line includes a plurality of delay cells connected in series The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal

Sriram Ganesan

Papers

Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation

Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof