A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance– only one $\tau $ (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm2/mg. Simulation results from the TFIT further validate the experimental results.

A 65 nm Temporally Hardened Flip-Flop Circuit

We introduce the 32 nm SOI Boeing Interleaved Flip-Flop, which is based on the DICE topology with additional RHBD layout enhancements. Sensitive node pairs were separated by interleaving elements of the flip-flop cell, to attain the required SEU performance while minimizing the area, speed and power impact. The Boeing Interleaved Flip-Flop takes advantage of the reduced charge sharing inherent to an SOI technology to maintain a two order of magnitude SEU improvement relative to the unhardened flip-flop, which corresponds to more than an order of magnitude SEU rate reduction compared to our 90 nm DICE.

Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing

We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the low-power (ACFF) and the highly-reliable (BCDMR) flip-flops. Its power dissipation is almost equivalent to the transmission-gate FF at 10% data activity while paying 3 × area penalty. Experiments by α-particle and neutron irradiation reveal its highly-reliable operations with no error at 1.2 V and 1 GHz. We measured five different process corner chips by α irradiation. Soft error rates are almost equivalent in these corner chips.

A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop

In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results.

Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection

The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

Sequential state elements for triple-mode redundant state machines, related methods, and systems

A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using it in a radiation hardened by design (RHBD) master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element incorporates redundancy to mask long transients, which would otherwise limit the circuit hardness. Two FF layouts using the proposed delay element are used in synthesis and auto-place and route experiments to confirm overall power, performance, and density. The first (interleaved) version uses a multi-bit cell interleaving the constituent circuits of four FFs. The second (inline) version interleaves the master and slave circuits to achieve high density while maintaining adequate critical node separation. The latter is shown to be more power efficient and the former is more robust to multiple node collection.

Srivatsan Chella

Papers

Temporal sequential logic hardening by design with a low power delay element