An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.

TCP/IP offload network interface device

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Fast-path apparatus for receiving data corresponding to a TCP connection

An interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host. The interface device includes hardware circuitry for processing network packet headers, and can use a dedicated fast-path for data transfer between the network and the storage unit, the fast-path set up by the host. The host CPU and protocol stack avoids protocol processing for data transfer over the fast-path, freeing host bus bandwidth, and the data need not cross the I/O bus, freeing I/O bus bandwidth. The storage unit may include RAID or other multiple drive configurations and may be connected to the INIC by a parallel channel such as SCSI or by a serial channel such as Ethernet or Fibre Channel. The interface device contains a file cache that stores data transferred between the network and storage unit, with organization of data in the interface device file cache controlled by a file system on the host. Additional interface devices may be connected to the host via the I/O bus, with each additional interface device having a file cache controlled by the host file system, and providing additional network connections and/or being connected to additional storage units.

Intelligent network storage interface system

A network interface device connected to a host provides hardware and processing mechanisms for accelerating data transfers between the host and a network. Some data transfers are processed using a dedicated fast-path whereby the protocol stack of the host performs no network layer or transport layer processing. Other data transfers are, however, handled in a slow-path by the host protocol stack. In one embodiment, the host protocol stack has an ISCSI layer, but a response to a solicited ISCSI read request command is nevertheless processed by the network interface device in fast-path. In another embodiment, an initial portion of a response to a solicited command is handled using the dedicated fast-path and then after an error condidtion occurs a subsequent portion of the response is handled using the the slow-path. The interface device uses a command status message to communicate status to the host.

Network interface device that fast-path processes solicited session layer read commands

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC or CPD provides a fast-path that avoids host protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC or CPD also assists the host for those message packets that are chosen for processing by host software layers. A communication control block (CCB) for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The CCB can be passed back to the host for message processing by the host. The INIC or CPD contains hardware circuits configured for protocol processing that can perform that specific task faster than the host CPU. One embodiment includes a processor providing transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Intelligent Network Interface System and Method for Protocol Processing

Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system (10) are disclosed herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system (10). These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system (10). In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses (50, 52, 54) which make up the bus arrangement. Systems (10) disclosed may include any number of individual buses within their bus arrangements. In one implementation, a system includes a single address bus (50) and two or more data buses (52, 54) such that different data transfers may be executed simultaneously on each data bus.

Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method

A crossbar routing arrangement is disclosed for use in a digital system having three or more buses. An associated method is also disclosed. The routing arrangement is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses and includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self-routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. The control arrangement cooperates with the switching arrangement to transfer the data subsets over physically distinct data transfer paths defined between the switching arrangement and the control arrangements. In accordance with one feature, the configuration of the routing arrangement provides for linear expansion whereby to service buses having increased width and/or to service an increased number of buses in a cost effective manner while, in either instance, maintaining high data throughput.

Linearly expandable self-routing crossbar switch

A method and associated arrangement for use in priority allocation in a bus interconnected digital multi-module system are disclosed. The modules are configured for requesting the use of the bus with each module being granted its request based upon its priority. During the operation of the system, a set of priorities is established such that the number of priorities is equal to the number of modules in the system. Each module is assigned to an initial priority. During the operation of the system, modules may be reassigned to a priorities which are different than their initial priorities. In addition, the priorities may be grouped in an initial group arrangement which may be reconfigured. The group arrangement may be reconfigured in any desired manner. Also, provisions are made for refusing a grant to a module even though that module possesses the highest priority among requesting modules.

Priority allocation in a bus interconnected discrete and/or integrated digital multi-module system

A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter, in a second or subsequent clock cycle, the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.

Stephen James Sheafor

Papers

Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method

Linearly expandable self-routing crossbar switch

Priority allocation in a bus interconnected discrete and/or integrated digital multi-module system

Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method

A bus arrangement and associated method in a computer system