Vitesse Semiconductor

About: Vitesse Semiconductor is a based out in . It is known for research contribution in the topics: Signal & Clock domain crossing. The organization has 224 authors who have published 209 publications receiving 3753 citations.

Forward error correction for 100 G transport networks

Abstract: The role of forward error correction has become of critical importance in fiber optic communications, as backbone networks increase in speed to 40 and 100 Gb/s, particularly as poor optical-signal-to-noise environments are encountered. Such environments become more commonplace in higher-speed environments, as more optical amplifiers are deployed in networks. Many generations of FEC have been implemented, including block codes and concatenated codes. Developers now have options to consider hard-decision and soft-decision codes. This article describes the advantages of each type in particular transmission environments.

InP Bipolar ICs: Scaling Roadmaps, Frequency Limits, Manufacturable Technologies

Abstract: Indium phosphide heterojunction bipolar transistors (HBTs) find applications in very wide-band digital and mixed-signal integrated circuits (ICs). Devices fabricated in high-yield process flows at 500 nm feature size obtain 450 GHz cutoff frequencies and 5 V breakdown and enable high yield fabrication of integrated circuits having more than 3000 transistors. Laboratory devices at 250 nm feature size obtain 755 GHz . We describe device and circuit bandwidth limits associated with HBTs, develop scaling roadmaps for HBTs having lithographic minimum feature sizes between 512 and 64 nm, and identify key technological challenges in realizing 480-GHz digital ICs and 1000-GHz amplifiers. Key features of manufacturable self-aligned dielectric sidewall processes are described in detail.

High speed cross point switch routing circuit with word-synchronous serial back plane

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

Product code based forward error correction system

Abstract: A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.

Multiple channel adaptive data recovery system

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.