An intensive study has been performed to understand and tune deep reactive ion etch (DRIE) processes for optimum results with respect to the silicon etch rate, etch profile and mask etch selectivity (in order of priority) using state-of-the-art dual power source DRIE equipment. The
research compares pulsed-mode DRIE processes (e.g. Bosch technique) and mixed-mode DRIE processes (e.g. cryostat technique). In both techniques, an inhibitor is added to
fluorine-based plasma to achieve directional etching, which is formed out of an oxide-forming (O2) or a fluorocarbon (FC) gas (C4F8 or CHF3). The inhibitor can be introduced together with the etch gas, which is named a mixed-mode DRIE process, or the inhibitor can be added in a
time-multiplexed manner, which will be termed a pulsed-mode DRIE process. Next, the most convenient mode of operation found in this study is highlighted including some remarks to
ensure proper etching (i.e. step synchronization in pulsed-mode operation and heat control of the wafer). First of all, for the fabrication ......
 Enjoy reading . Henri Jansen 18 June 2008

https://iopscience.iop.org/article/10.1088/0960-1317/19/3/033001/pdf

Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

Methods and devices for forming nanostructure monolayers and devices including such monolayers

Disclosed is an improved Reactive Ion Etch (RIE) technique for etching polysilicon or single crystal silicon as must be done in Very Large Scale Integration (VLSI) using silicon technology. It teaches the use of an etch gas that consists of a mixture of sulfur hexafluoride (SF 6 ) and chlorine (Cl 2 ) diluted with inert gas. This etch gas allows an RIE process which combines the very desirable features of selectivity (high Si/SiO 2 etch rate ratio) and directionality which creates vertical side walls on the etched features. Vertical side walls mean no mask undercutting, hence zero etch bias. It is particularly applicable to device processing in which micron or sub-micron sized lines must be fabricated to extremely close tolerances. It is a distinct improvement over wet chemical etching or plasma etching as it is conventionally applied.

Selective reactive ion etching of polysilicon against SiO2 utilizing SF6 -Cl2 -inert gas etchant

A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

Method for dicing a semiconductor wafer

Etching method using noble gas halides

Gas plasma vapor etching process utilized for removing portions of material from a semiconductor structure for a number of purposes including polishing and cleaning of the silicon wafers, finding pin holes in an insulating layer covering the semiconductor wafer and forming scribe lines in the wafer to thereafter permit the wafer to be mechanically broken into dice without any substantial damage to the dice

Stephen M Irving

Papers

Gas plasma vapor etching process