A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

Apparatus and method for implementing a multi-level memory hierarchy over common memory channels

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Memory channel that supports near memory and far memory access

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory These higher performance memory devices are referred to as “near memory” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Apparatus and method for implementing a multi-level memory hierarchy

A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.

Generation of far memory access signals based on usage statistic tracking

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Apparatuses and methods including memory and operation of same

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Apparatuses, devices and methods for sensing a snapback event in a circuit

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Interconnection for memory electrodes

An apparatus and a method for refreshing or toggling a phase-change memory cell are described. The apparatus includes a voltage ramp element coupled to the phase-change memory cell and provided for controlling voltage across the phase-change memory cell. A current control element is coupled to the phase-change memory cell and provided for controlling current through the phase-change memory cell. A current sensor element is coupled to the phase-change memory cell. A write-back timer and control element is coupled to the current sensor element and to the current control element.

Apparatus and method for refreshing or toggling a phase-change memory cell

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

Stephen Tang

Papers

Apparatuses and methods including memory and operation of same

Apparatuses, devices and methods for sensing a snapback event in a circuit

Interconnection for memory electrodes

Apparatus and method for refreshing or toggling a phase-change memory cell

Apparatuses, memories, and methods for address decoding and selecting an access line