An input resistor-diode protection circuit having an input resistor formed by a high impurity region within a deeper low impurity region, both a first conductivity type and input diode formed by the junction of the low impurity resistor region and the substrate along a substantial portion and a high impurity region overlapping the low impurity region at the output end of the resistor-diode circuit, both of a second conductivity type. A bipolar transistor connected to the output of the resistor in parallel to the diode also provides protection. A pair of concentric guard rings of first and second conductivity type laterally encompasses the input protection circuit.

ESD protection network for IGFET circuits with SCR prevention guard rings

A complementary metal-oxide semiconductor being comprised of at least one P channel MOSFET and at least one N channel MOSFET is disclosed. In the above semiconductor, -least one additional doped portion is formed close to at least one of the P and N channel MOSFETs at a small part of the region which is driven by the voltage supply. The additional doped! portion is directly connected to the voltage supply

Complementary metal-oxide semiconductor

A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices. The CMOS structure includes trenches between the individual transistor devices, and highly doped field regions are formed in the bottom of the trenches. Each N- and P-well includes a retrograde impurity concentration profile and extends beneath adjacent trenches.

Latch-up resistant CMOS structure for VLSI including retrograded wells

An IGFET is presented which includes a relatively low resistance path across the source-substrate junction to prevent parasitic bipolar effects while maintaining high component density in integrated circuits. The low resistance path across the source-substrate junction is formed by various methods including damaging the crystal structure at the junction interface, supplementing the damaged junction with a heavily doped region underlying the source region and spiking metallurgy. A particular application of the invention allows the prevention of latchup in CMOS devices. The invention also allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well as an ohmic contact to the underlying well or substrate.

Reducing bipolar parasitic effects in IGFET devices

A CMOS integrated circuit structure having an improved guardband configuration for the prevention of parasitic SCR latchup. Included with each guardband is a pair of field reducing surface regions of the opposite conductivity type to that of the guardband and situated one on each side of the guardband adjacent thereto. The field reducing regions which are electrically connected to each other serve to reduce any electric fields in the bulk region underlying the guardband thereby significantly improving the effectiveness of the guardband for collecting minority carriers in the bulk region to provide greater protection from latchup.

Complementary field-effect transistor integrated circuit device

The invention concerns CMOS integrated circuits including an arrangement to prevent regenerative bipolar current flow between complementary transistors in the circuit. In one particular form, the invention provides a CMOS inverter comprising an N-type substrate in which is formed a P-channel MOS transistor together with a P-type well having therein an N channel MOS transistor, the drain of the P-channel transistor being connected to the drain of the N-channel transistor, and there being disposed in the N-type substrate between the said transistors, a P-type region preferably extending to the depth of said P-type well and electrically connected to the source of the N-channel transistor. The effect of the P-type region aforesaid is to preclude the likelihood of regenerative bipolar conduction becoming established, in use of the inverter, in the substrate, which bipolar conduction might otherwise cause destruction of the CMOS circuit.

Stevenson Alastair Kershaw

Papers

CMOS monolithic integrated circuit

Monolithische integrierte cmos- schaltung