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Patent

CMOS monolithic integrated circuit

TLDR
In this paper, an N-type substrate is used to prevent regenerative bipolar current flow between complementary transistors in the circuit, where the drain of the P-channel MOS transistor is connected to the drain in the N-channel transistor by a P-type well.
Abstract
The invention concerns CMOS integrated circuits including an arrangement to prevent regenerative bipolar current flow between complementary transistors in the circuit. In one particular form, the invention provides a CMOS inverter comprising an N-type substrate in which is formed a P-channel MOS transistor together with a P-type well having therein an N channel MOS transistor, the drain of the P-channel transistor being connected to the drain of the N-channel transistor, and there being disposed in the N-type substrate between the said transistors, a P-type region preferably extending to the depth of said P-type well and electrically connected to the source of the N-channel transistor. The effect of the P-type region aforesaid is to preclude the likelihood of regenerative bipolar conduction becoming established, in use of the inverter, in the substrate, which bipolar conduction might otherwise cause destruction of the CMOS circuit.

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Citations
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ESD protection network for IGFET circuits with SCR prevention guard rings

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TL;DR: In this paper, a complementary metal-oxide semiconductor consisting of at least one P channel MOSFET and at least N channel MCFET is presented, where the additional doped portion is directly connected to the voltage supply.
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TL;DR: A complementary metal oxide semiconductor (CMOS) structure with the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices was proposed in this paper.
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Reducing bipolar parasitic effects in IGFET devices

TL;DR: In this article, a relatively low resistance path across the source-substrate junction is proposed to prevent parasitic bipolar effects while maintaining high component density in integrated circuits, which allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well or substrate.
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Complementary field-effect transistor integrated circuit device

TL;DR: In this article, a CMOS integrated circuit structure having an improved guardband configuration for the prevention of parasitic SCR latchup is presented, where a pair of field reducing surface regions of the opposite conductivity type to that of the guardband is included with each guardband.
References
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Patent

Input transient protection for integrated circuit element

TL;DR: In this paper, a PN junction bounding a current limiting resistor is coupled to a conductor and a distributed resistance is included within the resistor between the conductor and the PN boundary of the resistor.
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Complementary mosfet integrated circuit memory

TL;DR: In this article, a random access non-destructive voltage readout complementary MOSFET memory is fabricated on a single integrated circuit, including not only a plurality of identical memory cells arranged in a matrix array, but also the digital address decoding logic circuitry as well as the input/output buffer circuitry.
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High-voltage semiconductor integrated circuit

TL;DR: In this paper, a high-voltage semiconductor integrated circuit consisting of an N - -type substrate, a P +-type diffusion layer formed on the surface region of the substrate, an N +- type diffusion layer, and an N --type epitaxial layer, forming a high voltage-proof transistor against voltage more than one thousand and several hundred volts.