Analysis of the impact of digital watermarking on computer-aided diagnosis in medical imaging

In this paper, field programmable gate array (FPGA) implementation of reversible watermarking (RW) algorithm by histogram bin shifting (HBS) that can be used for real-time applications of medical and military images has been presented. As the tolerance level of distortion has to be minimal, RW scheme is necessary here. The reversible mode of the process helps in extracting both the original image and the watermark at the receiver end after undergoing through embedding and decoding procedure. The embedded watermark contains the underlying security information of the host images in case of any infringement. Although software implementations of RW schemes are available, very few attempts have been made for hardware realizations of such schemes. The inherent delay associated with software implementations can be minimized by using an on-chip hardware that performs the watermarking process immediately after capturing the image in real time. In this paper, the embedding and decoding procedures involved in the watermarking scheme are implemented using Xilinx System Generator and carries out a detailed design and analysis of the hardware architectures required for the embedding and extraction processes. The device utilization results for both the embedding and decoding process is low and practically viable. The maximum operating frequency for embedding and extraction processes are 445.330 and 201.824 MHz, respectively, which shows improved performance results over similar existing research work in the literature. The power consumptions for embedding and extraction processes are found to be 1.215 and 0.104 W, respectively. To the best of our knowledge, this is the first FPGA-based hardware implementation of RW by HBS.

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time

In this paper a new approach for designing invisible non-blind full crypto-watermarking system targeting images security on FPGA platform is presented. This new design is based on the Hardware-Software co-design approach using the High-Level Synthesis (HLS) tool of Xilinx which allows a good compromise between development time and performances. For a better authentication and robustness of the proposed system, the Discrete Wavelet Transform (DWT) is employed. To more enhance the security level, a new chaos-based generator proposed is integrated into a stream cipher algorithm in order to encrypt and decrypt the watermark during the insertion and extraction phases.This approach allows a better secure access at the positions of the watermark and to distribute the watermark evenly throughout the image. Three novel customized Intellectual Property (IP) cores designed under HLS tool, implementing Haar DWT and the new chaos-based key generator, have been generated, tested, and validated. The generated Register Transfer Level-IP (RTL-IP) cores are integrated into a Vivado library that achieves real-time secured watermarking operations for both embedding and extraction processes. The system has been evaluated using the main metrics in terms of imperceptibility of the produced watermarked images achieving a Peak Signal to Noise Ratio (PSNR) of 47 dB, robustness against most geometric and image processing attacks achieving a Normalized Cross-Correlation (NCC) of 0.99. The proposed crypt-watermarking system allows a good solution against brute force attack which produce a huge key-space of $$2^{768}$$
 . Finally, the implementation offers a good efficiency value of 0.19 MHz/LUT in terms of FPGA resource consumption and speed, making the system a reliable choice for real sensitive embedded applications.

Real-time FPGA implementation of a secure chaos-based digital crypto-watermarking system in the DWT domain using co-design approach

Reversible watermark combining pre-processing operation and histogram shifting

Digital down converter (DDC) is one of the crucial components in digital radio receiver. The working function of DDC is to convert the frequency translation from Intermediate Frequency (IF) band to baseband signal. This paper briefs a hardware efficient DDC architecture which is made of COordinate Rotation Digital Computer (CORDIC) processor act as a digital oscillator followed by multi-stage Cascaded Integrator Comb (CIC) performs as a high rate decimation filter and then Multi-channel Systolic Finite Impulse Response (MSFIR) decimation filter allows perfect output. All of these components of the proposed DDC architecture have been designed in Xilinx ISE 14.7 simulator using optimization techniques and targeted to the Xilinx Kintex-7 Field Programmable Gate Array (FPGA) device. Implementation of DDC on FPGA provides high flexibility, moderate cost and customizability. The result analysis of the proposed DDC model is superior to the similar design with regard to area, operating speed and power consumption. The implemented DDC design is used to transform input bandwidth from about 70 MHz to 137 kHz, matching in Software Defined Radio (SDR) system requirements.

FPGA implementation of high performance digital down converter for software defined radio

The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block $$(8 \times 8)$$
 , the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed.

VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

This paper presents a VLSI architecture of rhombus interpolation based reversible watermarking by difference expansion. The proposed architecture have been implemented and tested on Xilinx Virtex-7 FPGA, Zynq SoC (System On Chip) and ultra-scale FPGA platforms. The system is based on the modified rhombus interpolation scheme to embed and extract the copyright protection for medical and military imaging applications. In the reversible watermarking, the embedded watermark can be completely extracted along with the original image in a lossless manner. The experimental result of the proposed architectures of the encoding and decoding process for reversible watermarking is implemented using VIVADO 2014.2. The results for quality factors of the original and watermarked image is obtained using MATLAB R2013a and compared with the result generated from hardware implementation in FPGA, SoC and Ultra-scale platform. The results show the viability of low cost, high speed and real-time use of the proposed VLSI architecture.

FPGA and SoC based VLSI architecture of reversible watermarking using rhombus interpolation by difference expansion

In this paper an adaptive feedback based Reversible Watermarking (RW) algorithm using Difference Expansion (DE) is designed for gray-scale still pictures. The algorithm obtains automatically the highest payload size and the corresponding embedding threshold and also determines the best watermarked picture for an input cover picture with respect to the quality metric Peak-Signal-to-Noise Ratio (PSNR). These automatically obtained parameters are non-user-defined like other non-feedback based RW algorithms. The payload that can be embedded into a cover image is discussed, and a feedback mechanism to control this size is designed. Software implementation results using MATLAB 2013b for ten tested images are presented and compared with each other based on their quality metrics. The proposed algorithm is then compared with existing non-feedback based RW algorithms. These results indicate that the proposed algorithm has low timing complexity over other existing non-feedback based RW algorithms which in turn provide higher speed.

An adaptive feedback based reversible watermarking algorithm using difference expansion

The additional operation of retrieval of the cover image at the decoder is necessary for lossless watermarking system. Taking into account this major issue, efficient implementation of reversible image watermarking needs to be addressed. This can be solved using hardware implementation. This paper focus on the digital design with pipelined architecture of reversible watermarking algorithm based on Difference Expansion (DE) which is linear and whose running time is O (n). There are three different digital architectures proposed in this paper namely dataflow architecture, optimized dataflow architecture using pipelining and the modified architecture using pipelining. All the three design is implemented on Xilinx based FPGA. To the best of our knowledge this is the first digital design and pipelined architecture proposed in the literature for reversible watermarking using difference expansion.

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

This paper presents a reversible image watermarking (RIW) method including an adaptive feedback part based on difference expansion (DE) With respect to some parameters of the image, peak signal to noise ratio (PSNR), the highest payload capacity and the corresponding embedding threshold are spontaneously calculated by using the proposed adaptive feedback-based reversible Image watermarking (AFRIW) The payload capacity for data embedding is briefly explained The machinery part of the adaptive feedback for controlling the payload capacity is presented Software verification of three cover images is presented Based on some image parameters, the comparative result between the proposed AFRIW algorithm and DE-based RIW method is presented This paper also presents the VLSI architecture of this proposed algorithm for RIW The proposed architecture has been implemented using VIVADO 20162 based on Xilinx Virtex-7 FPGA and Zynq device platforms The software implementation results clearly demonstrated that the AFRIW method provides higher PSNR than the DE-based RIW method The hardware implementation results indicate that the proposed algorithm has low timing complexity over other existing feedback based RIW algorithms which in turn provide higher speed

Subhajit Das

Papers

VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

FPGA and SoC based VLSI architecture of reversible watermarking using rhombus interpolation by difference expansion

An adaptive feedback based reversible watermarking algorithm using difference expansion

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

Hardware implementation of adaptive feedback based reversible image watermarking for image processing application