This paper proposes a method for the detection and classification of multiple events in an electrical power system in real-time, namely; islanding, high frequency events (loss of load), and low frequency events (loss of generation). This method is based on principal component analysis of frequency measurements and employs a moving window approach to combat the time-varying nature of power systems, thereby increasing overall situational awareness of the power system. Numerical case studies using both real data, collected from the U.K. power system, and simulated case studies, constructed using DigSilent PowerFactory, for islanding events, as well as both loss of load and generation dip events, are used to demonstrate the reliability of the proposed method.

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Real-Time Multiple Event Detection and Classification Using Moving Window PCA

This paper proposes a novel approach that combines specialized pairwise classifiers trained with different feature subsets for facial expression classification. The proposed approach first detects and extracts automatically faces from images. Next, the face is split into several regular zones and textural features are extracted from each zone to capture local information. The features extracted from all zones are concatenated to model the whole face. A pairwise approach that considers all pairs of classes and a hybrid feature selection strategy is used to both reduce the dimensionality and to select relevant features to discriminate between specific pairs of classes. Several pairwise classifiers are then trained with such pairwise feature subsets. At the end, given a new face image, all features are extracted from such a face, but only the previously selected subset of features is inputted to each pairwise classifier. The output of all pairwise classifiers is combined using a majority voting rule to decide on the facial expression. Experiments have been carried out on three publicly available datasets (JAFFE, CK and TFEID) and the correct classification rates of 99.05%, 98.07% and 99.63% were achieved respectively. Therefore, the pairwise approach is effective to discriminate between different facial expressions and the results achieved by the proposed approach are slightly better than several current approaches.

Facial expression recognition using a pairwise feature selection and classification approach

Automated human emotion detection is a topic of significant interest in the field of computer vision. Over the past decade, much emphasis has been on using facial expression recognition (FER) to extract emotion from facial expressions. Many popular appearance-based methods such as local binary pattern (LBP), local directional pattern (LDP) and local ternary pattern (LTP) have been proposed for this task and have been proven both accurate and efficient. In recent years, much work has been undertaken into improving these methods. The gradient local ternary pattern (GLTP) is one such method aimed at increasing robustness to varying illumination and random noise in the environment. In this paper, GLTP is investigated in more detail and further improvements such as the use of enhanced pre-processing, a more accurate Scharr gradient operator, dimensionality reduction via principal component analysis (PCA) and facial component extraction are proposed. The proposed method was extensively tested on the CK+ and JAFFE datasets using a support vector machine (SVM) and shown to further improve the accuracy and efficiency of GLTP compared to other common and state-of-the-art methods in literature.

/pdf/improved-gradient-local-ternary-patterns-for-facial-2mqjpsozzc.pdf

Improved gradient local ternary patterns for facial expression recognition

Face Recognition is the ability to detect and recognize a person by their facial characteristics. Face is a multidimensional and hence requires a lot of mathematical computations. Face recognition system is very essential and important for providing security, mug shot matching, law enforcement applications, user verification, user access control, etc and is mostly used for recognition for various applications. These all applications require an efficient Face recognition system. There are many methods that are already proposed and have low recognition capability, high false alarm rate. Hence the major task of the research is to develop face recognition system with improved accuracy and improved recognition time of an face recognition system. This paper proposes a hybrid face recognition algorithm by combining two face recognition techniques by integrating (PCA) principle Component Analysis, (LDA) Linear Discriminant Analysis. Jacobi method is used to compute Eigenvector that are necessary for PCA and LDA algorithms. Face Recognition system will be implemented on Embedded system based Raspberry pi 3 board.

Real-time implementation of face recognition system

In everyday interaction, our face is the basic and primary focus of attention. Out of many human psycho-signatures, the face provides a unique identification of a person by the virtue of its size, shape, and different expressions such as happy, sad, disgust, surprise, fear, anger, neutral, etc. In a human computer interaction, facial expression recognition is an interesting and one of the most challenging research areas. In the proposed work, principle component analysis (PCA) and independent component analysis (ICA) are used for the facial expressions recognition. Euclidean distance classifier and cosine similarity measure are used as the cost function for testing and verification of the images. Japanese Female Facial Expression (JAFFE) database and our own customized database are used for the analysis. The experimental result shows that ICA provides improved facial expression recognition in comparison with PCA. The PCA and ICA provides detection accuracy of 81.42 and 94.28 %, respectively.

Performance Evaluation of PCA and ICA Algorithm for Facial Expression Recognition Application

The face being the primary focus of attention in social interaction plays a major role in conveying identity and emotion. A facial recognition system is a computer application for automatically identifying or verifying a person from a digital image or a video frame from a video source. The main aim of this paper is to analyse the method of Principal Component Analysis (PCA) and its performance when applied to face recognition. This algorithm creates a subspace (face space) where the faces in a database are represented using a reduced number of features called feature vectors. The PCA technique has also been used to identify various facial expressions such as happy, sad, neutral, anger, disgust, fear etc. Experimental results that follow show that PCA based methods provide better face recognition with reasonably low error rates. From the paper, we conclude that PCA is a good technique for face recognition as it is able to identify faces fairly well with varying illuminations, facial expressions etc.

Face recognition and facial expression identification using PCA

Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.

Superconductor Standard Cell Library for Advanced EDA Design

In design and layout of rapid single flux quantum circuits, multiple independent biases are often desired to provide flexibility in timings of critical paths. In absence of automated power routing, power nets are often included as part of the layout cells. Multiple variants of each cell need to be manually created to support different biasing configurations. The parametric approach for routing power nets provides the flexibility to dynamically change biasing configurations, based on the same parametric cell. Multiple cells in a circuit block can be configured to be connected to a single power net or can be biased using several independent power nets. With the goal of minimizing the cell size, it is often difficult to maintain rotational symmetry for the power and passive transmission line (PTL) tracks. The parametric approach also enables rotating the cell while avoiding misalignment of the tracks. In addition, our implementation can dynamically add moat bridges to connect ground planes isolated by moats. This is especially useful to bridge very long moats that span two or more adjacent cells. Furthermore, this approach of dedicated tracks for power and PTL routing is also more amenable to design automation.

Parametric Approach for Routing Power Nets and Passive Transmission Lines as Part of Digital Cells

HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years  The design infrastructure includes the process design kit, advanced simulation methodology, and IC verification rule decks The superconductor hierarchical circuit analyzer developed by HYPRES serves as bedrock of our simulation methodology facilitating circuit analysis and debugging including extraction of circuit parameter margins, analysis of Monte-Carlo simulations with process corners, as well as automated timing characterization Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics    Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence (PRBS) generator as reference circuits, we demonstrate the use of Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker and layout-versus-schematic checker

Development of Superconductor Advanced Integrated Circuit Design Flow Using Synopsys Tools

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Sukanya Sagarika Meher

Papers

Face recognition and facial expression identification using PCA

Superconductor Standard Cell Library for Advanced EDA Design

Parametric Approach for Routing Power Nets and Passive Transmission Lines as Part of Digital Cells

Development of Superconductor Advanced Integrated Circuit Design Flow Using Synopsys Tools

Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library