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Display screen or portion thereof with graphical user interface

A key step in the Advanced Encryption Standard (AES) algorithm is the “S-box.” Many implementations of AES have been proposed, for various goals, that effect the S-box in various ways. In particular, the most compact implementations to date of Satoh et al.[14] and Mentens et al.[6] perform the 8-bit Galois field inversion of the S-box using subfields of 4 bits and of 2 bits. Our work refines this approach to achieve a more compact S-box. We examined many choices of basis for each subfield, not only polynomial bases as in previous work, but also normal bases, giving 432 cases. The isomorphism bit matrices are fully optimized, improving on the “greedy algorithm.” Introducing some NOR gates gives further savings. The best case improves on [14] by 20%. This decreased size could help for area-limited hardware implementations, e.g., smart cards, and to allow more copies of the S-box for parallelism and/or pipelining of AES.

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A very compact s-box for AES

We propose a new 64-bit blockcipher Piccolo supporting 80 and 128-bit keys Adopting several novel design and implementation techniques, Piccolo achieves both high security and notably compact implementation in hardware We show that Piccolo offers a sufficient security level against known analyses including recent related-key differential attacks and meet-in-the-middle attacks In our smallest implementation, the hardware requirements for the 80 and the 128-bit key mode are only 683 and 758 gate equivalents, respectively Moreover, Piccolo requires only 60 additional gate equivalents to support the decryption function due to its involution structure Furthermore, its efficiency on the energy consumption which is evaluated by energy per bit is also remarkable Thus, Piccolo is one of the competitive ultra-lightweight blockciphers which are suitable for extremely constrained environments such as RFID tags and sensor nodes

/pdf/piccolo-an-ultra-lightweight-blockcipher-1vh23tr717.pdf

Piccolo: an ultra-lightweight blockcipher

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.

/pdf/high-speed-vlsi-architectures-for-the-aes-algorithm-4slr3bjvln.pdf

High-speed VLSI architectures for the AES algorithm

We propose a new 128-bit blockcipher CLEFIA supporting key lengths of 128, 192 and 256 bits, which is compatible with AES. CLEFIA achieves enough immunity against known attacks and flexibility for efficient implementation in both hardware and software by adopting several novel and state-of-the-art design techniques. CLEFIA achieves a good performance profile both in hardware and software. In hardware using a 0.09 μm CMOS ASIC library, about 1.60 Gbps with less than 6 Kgates, and in software, about 13 cycles/byte, 1.48 Gbps on 2.4 GHz AMD Athlon 64 is achieved. CLEFIA is a highly efficient blockcipher, especially in hardware.

/pdf/the-128-bit-blockcipher-clefia-extended-abstract-488t7elast.pdf

The 128-Bit Blockcipher CLEFIA (Extended Abstract)

Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5.4 Kgates is obtained for a 128-bit key Rijndael circuit using a 0.11-µm CMOS standard cell library. It requires only 0.052 mm2 of area to support both encryption and decryption with 311 Mbps throughput. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.6 Gbps for a high-speed implementation whose size is 21.3 Kgates.

/pdf/a-compact-rijndael-hardware-architecture-with-s-box-9gulysniid.pdf

A Compact Rijndael Hardware Architecture with S-Box Optimization

Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 µW at 10 MHz using 0.13 µm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 µW, respectively.

/pdf/an-optimized-s-box-circuit-architecture-for-low-power-aes-b9hmw9k547.pdf

An Optimized S-Box Circuit Architecture for Low Power AES Design

A data storage device includes an encryption circuit for encrypting desired data and personal identification information by use of an encryption key created out of a given piece of the personal identification information such as a password, a magnetic disk for recording the data and the personal identification information which are encrypted by the encryption circuit, and a central processing unit for executing user verification by use of the encrypted personal identification information stored in the magnetic disk. The user verification is executed based on such verification data. The write data transmitted from a host system are encrypted by use of the foregoing encryption key and are recorded in the magnetic disk. Alternatively, the data read out of the magnetic disk are decrypted by use of the encryption key and are transmitted to the host system.

Information processing with data storage

This paper describes compact and high-speed hardware architectures for the 128-bit block ciphers AES and Camellia, and reports on their performances as implemented using ASIC libraries and an FPGA chip. A 3-key triple-DES implementation is included for comparison. Small S-Box hardware de-signs using composite field inverters are also described, and are contrasted with conventional S-Boxes generated from truth tables. In comparison with prior work, our architectures obtained the smallest gate counts and the highest throughputs for both of the ciphers. The smallest designs were 5.32 Kgates with a throughput of 235 Mbps for the AES, 6.26 Kgates with 204 Mbps for Camellia, and 5.74 Kgates with 170 Mbps for the triple-DES by using a 0.18-μm library. The highest throughputs of 3.46 Gbps with 36.9 Kgates, 2.15 Gbps with 29.8 Kgates, and 1.07 Gbps with 17.0 Kgates were obtained for the AES, Camellia, and triple-DES respectively, using a 0.13-μm library.

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES

We proposed unified hardware architecture for the two 128-bit block ciphers AES and Camellia, and evaluated its performance using a 0.13-μm CMOS standard cell library. S-Boxes are the biggest hardware components in block ciphers, and some times they consume more than half of the design area. The S-Boxes in AES and Camellia are the combination of affine transformations and multiplicative inversions on a Galois fields. The size of the fields is same, but their structures are different. Therefore we converted the basis between the fields by using isomorphism transformations, and shared the inverter between AES and Camellia. The affine transformations were also merged by factoring common terms. In addition to the S-Box sharing, many other components such as permutation layers and key whiting are also merged. As a result, a compact hardware of 14.9K gates with throughputs of 469 Mbps for AES and of 661 Mbps for Camellia was achieved. The hardware synthesized with speed optimization obtained throughputs of 794 Mbps and 1.12 Gbps for each algorithm with 24.4K gates.

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Sumio Morioka

Papers

A Compact Rijndael Hardware Architecture with S-Box Optimization

An Optimized S-Box Circuit Architecture for Low Power AES Design

Information processing with data storage

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES

Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia