In general, techniques are described for efficiently implementing application identification within network devices. In particular, a network device includes a control unit that stores data defining a group Deterministic Finite Automata (DFA) and an individual DFA. The group DFA is formed by merging non-explosive DFAs generated from corresponding non-explosive regular expressions (regexs) and fingerprint DFAs (f-DFAs) generated from signature fingerprints extracted from explosive regexs. The non-explosive regexs comprise regexs determined not to cause state explosion during generation of the group DFA, the signature fingerprints comprise segments of explosive regexs that uniquely identifies the explosive regexs, and the explosive regexs comprise regexs determined to cause state explosion during generation of the group DFA. The network device includes an interface that receives a packet and the control unit traverses first the group DFA and then, in some instances, the individual DFAs to more efficiently identify network applications to which packets correspond.

Efficient application identification with network devices

An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

Using storage cells to perform computation

Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Hierarchical immutable content-addressable memory processor

Systems for hardware-accelerated lossless data compression are described. At least some embodiments include data compression apparatus that includes a plurality of hash memories each associated with a different lane of a plurality of lanes (each lane including data bytes of a data unit being received by the compression apparatus), an array including array elements each including a plurality of validity bits (each validity bit within an array element corresponding to a different lane of the plurality of lanes), control logic that initiates a read of a hash memory entry if a corresponding validity bit indicates that said entry is valid, and an encoder that compresses at least the data bytes for the lane associated with the hash memory comprising the valid entry if said valid entry comprises data that matches the lane data bytes.

Hardware-Accelerated Lossless Data Compression

A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Content addressable memory with programmable word width and programmable priority

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Content addressable memory device

A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plurality of address values are queued within the first-in-first-out storage circuit to enable the address values to be read in succession by an external device.

Block-writable content addressable memory device

Entry relocation in a content addressable memory (CAM) device. The CAM device is instructed to store a first value and to supply an address at which the first value is stored. If the address indicates that the first value has been stored within an overflow storage array of the CAM device, the CAM device is instructed to store the first value again.

Sunder R. Rathnavelu

Papers

Content addressable memory device

Block-writable content addressable memory device

Entry relocation in a content addressable memory device

Content addressable memory with hashing function