A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Semiconductor memory device and method of operating the same

In general, techniques are described for efficiently implementing application identification within network devices. In particular, a network device includes a control unit that stores data defining a group Deterministic Finite Automata (DFA) and an individual DFA. The group DFA is formed by merging non-explosive DFAs generated from corresponding non-explosive regular expressions (regexs) and fingerprint DFAs (f-DFAs) generated from signature fingerprints extracted from explosive regexs. The non-explosive regexs comprise regexs determined not to cause state explosion during generation of the group DFA, the signature fingerprints comprise segments of explosive regexs that uniquely identifies the explosive regexs, and the explosive regexs comprise regexs determined to cause state explosion during generation of the group DFA. The network device includes an interface that receives a packet and the control unit traverses first the group DFA and then, in some instances, the individual DFAs to more efficiently identify network applications to which packets correspond.

Efficient application identification with network devices

An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Multiple independent serial link memory

An apparatus and method for performing logical operations on information in the communications protocol stack, such as the transport layer (L4) port numbers, characterizing a received packet or frame of data in a data communications device such as a router or switch. The results of the logical operations, along with other packet/frame-identifying data, are used to generate a more efficient lookup key. A content addressable memory (CAM) lookup is used to determine the action indicated by the rules defined by a rule-based routing or switching scheme, such as an access control list (ACL). The results of these logical operations extend the key space and thus provide a finer-grained match between the original, unextended input key and a rule action, thereby pointing to a rule action precisely tailored to packet processing. The rule can thus be applied with fewer CAM entries, providing the versatility improvement and CAM cost reduction necessary to keep up with the ever-increasing rule complexity requirements of advanced data communication and internetworking systems. An embodiment utilizing asymmetrical processing of packets, depending on whether the packet is inbound to the data communications device or outbound from it, is also disclosed. Furthermore, a ternary content-addressable memory (TCAM) implementation is disclosed. Use of a TCAM for ACL or other rule lookups further enhances the efficiency of rule processing by providing a masking capability for each TCAM entry which can be used to provide an additional level of flexibility for rule element checking.

Logical operation unit for packet processing

In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Non- volatile semiconductor memory with page erase

A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Content addressable memory with configurable class-based storage partition

A CAM device having a plurality of CAM blocks is partitioned into a number of individually searchable partitions, where each partition may include one or more CAM blocks of the CAM device. In one embodiment, each CAM block is connected to a block select circuit that stores a class code indicating what class or type of data is stored in the block. The same class code may be stored in any number of block select circuits to define a partition as including the corresponding number of CAM blocks. During compare operations between a comparand word and data stored in the CAM device, a search code is provided to the block select circuits. Each block select circuit compares the search code with its class code and, in response thereto, selectively enables or disables the corresponding CAM block for the compare operation. In some embodiments, the block select circuit enables the corresponding CAM block if the search class matches the class code and, conversely, disables the corresponding CAM block if the search code does not match the class code.

Method and apparatus for partitioning a content addressable memory device

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Content addressable memory device

Rows of a CAM array are partitioned into a plurality of row segments, with each row segment having a corresponding match line segment. A first match line segment is pre-charged to enable detection of match conditions in the associated first row segment. Subsequent match line segments are then selectively charged in response to the match conditions in the preceding row segments. In one embodiment, rows of a CAM array are partitioned into first and second row segments. A first match line segment is pre-charged to enable detection of match conditions within the associated first row segment. If there is a match condition in the first row segment, a second match line segment is charged to enable detection of match conditions in the associated second row segment. If there is a match condition in the second row segment, a match condition is indicated for the row. If there is not a match condition in the second row segment, a mismatch condition is indicated for the row. Conversely, if there is not a match condition in the first row segment, the second match line segment is not charged, thereby disabling the second match line segment. In this manner, a mismatch condition may be indicated for the row without pre-charging the second match line segment.

Selective match line pre-charging in a partitioned content addressable memory array

A method and apparatus hierarchically cascades a number of memory devices to achieve a balance between the number of match flag inputs and the time required to generate the system match flag. In some embodiments, the number of match inputs required for each cascaded device and the time required to generate a system match flag are each logarithmically related to the number of cascaded devices. In one embodiment, an m-level hierarchy of groups are defined for up to n memory devices, where m=log2n and m is an integer greater than 2. The first hierarchy is defined as including n/2 groups of 2 memory devices, the second hierarchy is defined as including n/4 groups of 4 memory devices, and so on, until a final hierarchy of one group is defined. Each group in a given hierarchical level includes a pair of groups from the preceding hierarchical level. At each hierarchical level, the match flag generated by the first of the group's pair may be provided to each of the CAM devices in the second of the group's pair. In other embodiments, at each hierarchical level, the match flag(s) generated by devices in the first of the pair defined in the previous hierarchical are selectively provided to devices in the second of the pair defined in the previous hierarchical level.

Jose Pio Pereira

Papers

Content addressable memory with configurable class-based storage partition

Method and apparatus for partitioning a content addressable memory device

Content addressable memory device

Selective match line pre-charging in a partitioned content addressable memory array

Hierarchical depth cascading of content addressable memory devices