In this work, we are making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor. It is observed that LVCMOS12 is the most energy efficient than all available LVCMOS having 26.23, 58.37 and 75.65 % less IO power reduction than LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 1 GHz. Then we are making this ALU portable using MOBILE DDR IO standard in place of default LVCMOS33 IO standard which we use in traditional ALU. As we replace LVCMOS with MOBILE DDR, we are achieving 69.07 % portability in terms of IO power and 29.36 % in terms of Leakage power at 2.9 GHz. In next stage, we try to enhance the performance of ALU with MOBILE DDR but not beyond the power consumption with LVCMOS. In that way, we achieve the highest frequency of 12 GHz with MOBILE DDR. That was earlier possible for 3.8 GHz 64-bit ALU using CMOS. In this HDL based implementation of 64-bit ALU on FPGA, Kintex-7 FPGA is used with XC7K70T device and FBG676 package is used.

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA

There are many areas of communication and network, which have open scope to use FIR filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with less delay and latency will increase performance of network. In this work, we are going to design an FIR filter that will energy efficient as well as faster than traditional design. Three different FPGA and SOC are taken under consideration and our design is implemented on these four ICs and we find the most energy efficient architecture and also find the architecture that will deliver highest performance among these four architectures taken under consideration. There is 47.74% reduction in latency when we migrate our FIR Filter design from 28 nm process technology based seven series architecture to 20 nm process technology based ultrascale architecture. When we analyze power dissipation of Artix-7, Kintex-7, Zynq and Ultrascale FPGA then we conclude that Zynq 7000 All programmable SOC is power hungry architecture and Kintex ultrascale architecture is the most energy efficient architecture that dissipates 20.86% less power than Zynq 700 All programmable SOC. For performance evaluation, we have taken benchmark C code of FIR provide by Xilinx. We transform that C code into HDL using Vivado HLS 2016.2 before power analysis on Vivado 2016.2. Ultrascale FPGA is generally used for packet processing in 100G networking and heterogeneous wireless infrastructure.

Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

In this work, we are using voltage scaling to make the counter design as an energy efficient design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL and CMOS logic families. In addition to performing the counting function, it can be cleared or loaded in parallel. It has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs. Out of which in case of clock the maximum power dissipation is in range of 12.126W to 35.056W at which is in case of 1THz when measured at different voltage levels where as in case of IOs the maximum power dissipation is in range of 20.636W to 25.031W. Which is again in case of 1THz when measured at different voltage levels. There is not much significant change in case of signal and leakage power at different voltage levels. The maximum total power dissipation is in range of 33.887W to 67.986W at frequency of 1THz when operated at different voltages. Also there can be 94.45% to 99.61% reduction in total power dissipation if we operate on frequency of 1MHz instead of frequency of 1THz at different Voltage levels.

Energy Efficient Counter Design Using Voltage Scaling on FPGA

FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

Green communication is the latest research trend practiced by researcher in green computing and network communication. There is no extensive work in green network design and no work in thermal aware network equipment design. In order to fill this research gap, we are going to design thermal aware energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for thermal aware green communication. We had achieved 59.32% to 72.96% reduction when temperature varies from 15°C to 75°C and airflow is 250 Linear Feet Per Minute (LFM), and reduction is in range of 59.30% to 72.97%, when temperature varies from 15°C to 75°C and airflow is 500 LFM. This design is implemented on Virtex 6 Field programmable Gate Array (FPGA) using Verilog.

Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA

When we conserve energy resources from any systems, our environment can enjoy cleaner air and a healthier, and we can help protect the climate by reducing heating due to more energy consumption. Energy Efficient medical equipment design is the latest research in medical science. Now, scientists are focus and shifting toward energy efficient medical system design. ECG machine is the most commonly used in medical equipments. If any equipment consuming less power than the environment, climate and whole medical regions will be move to greener, pollution-less and energy efficient. Finally, it reduces the cost of medical treatment and save energy consumptions. In this work, we are going to design and implement energy efficient ECG machine using LVDCI (Low Voltage Digitally Control Impedance), SSTL (Stub Series Terminated Logic) and HSTL (High Speed Transistor Logic) I/O standard.

Green ECG Machine Design Using Different Logic Families

Capacitance Scaling Based Energy Efficient and Tera Hertz Design of Malayalam Unicode Reader on FPGA

In this paper, we design energy efficient Finite Impulse Response (FIR) filter, which is widely used in wireless sensor networks as a signal pre-processing step because sensor nodes require a long working periods. Finite impulse response (FIR) filter is a type of digital filters. Response to a unit impulse is finite in FIR filter. FIR filter avoids the limitation of old parallel algorithm which take huge amount of hardware resources and its output as a weighted sum of its present and past input value. In this paper, wireless sensor network frequencies are used and obtain a maximum power reduction. It has been observed that the maximum total power reduction occurs in the case of wireless sensor network for scale down of frequency from 2.4 GHz to 16MHz. When it is operating with LVCMOS33, the maximum reduction is 1.252W. So, it is preferable to operate the circuit at the wireless frequency of 16MHz with respect to other wireless frequencies to make it more energy efficient.

Wireless sensor network specific low power FIR filter design and implementation on FPGA

In this work, we are using voltage scaling and frequency scaling In voltage scaling, voltage is scaled from 3V to 1V, where intermediate values are 25V, 2V, 18V and 15V In frequency scaling, frequency is scaled from 1 MHz to 1 THz, where intermediate values are 10 MHz, 100 MHz, 1 GHz, 10 GHz and 100 GHz When we scale down device operating frequencies from 1THz to 1GHz, there is 729% reduction in power dissipation on Virtex-6 FPGA When we scale down device operating frequencies from 1THz to 1GHz, there is 9875% reduction in power dissipation on Virtex-4 FPGA When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 8223%, 9683%, 9845% and 99% reduction in power dissipation respectively on Virtex-6 FPGA on 10MHz device operating frequency When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 7442%, 9267%, 9471% and 9766% reduction in power dissipation respectively on Virtex-6 FPGA on 1THz device operating frequency

http://ieeexplore.ieee.org/iel7/7109473/7115730/07115855.pdf

Sunny Singh

Papers

Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA

Green ECG Machine Design Using Different Logic Families

Capacitance Scaling Based Energy Efficient and Tera Hertz Design of Malayalam Unicode Reader on FPGA

Wireless sensor network specific low power FIR filter design and implementation on FPGA

Energy efficient flip flop design using voltage scaling on FPGA